Patents by Inventor Paul Findley

Paul Findley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8276259
    Abstract: A method of constructing a differential inductor having a high self-resonance frequency is provided. In general, a ground point is identified. A first coil having a first and second loop is created such that the first loop is electrically further away from the ground point than the second loop. A second coil having a third and fourth loop are created such that the third loop is electrically further away from the ground point than the second loop. The first coil and the second coil are positioned such that the first loop is positioned as a near neighbor to said fourth loop and said second loop is positioned as a near neighbor to said third loop.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: October 2, 2012
    Assignee: RF Micro Devices, Inc.
    Inventors: Paul Findley, Jon Tao, Gholam-Ali Rezvani
  • Patent number: 6972658
    Abstract: A differential inductor is formed from branch coils that are staggered with respect to one another rather than concentrically coiled within one another. Each coil is formed from conductive strips. The conductive strips with the largest voltage swings thereon are shielded from one another by conductive strips with lower voltage swings thereon. This shielding allows the effective capacitance of the differential inductor to be lowered, which in turn raises the range of frequencies at which the differential inductor can operate.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: December 6, 2005
    Assignee: RF Micro Devices, Inc.
    Inventors: Paul Findley, Jon Tao, Gholam-Ali Rezvani
  • Patent number: 5994766
    Abstract: A circuit arrangement for a flip chip utilizes fixed potential shield traces between various signal traces in a redistribution layer to decrease coupling impedances and crosstalk within the layer. In particular, by orienting a fixed potential shield trace between a pair of signal traces and/or between a pair of differential trace pairs, capacitive coupling between the traces is greatly reduced, thereby permitting the signal traces to be routed closer to one another than would be possible if the shield trace was omitted. Often, minimum line width and spacing design rules may be met to ensure maximum circuit density for the redistribution layer and the associated device interconnections, and without concern for excessive adverse effects due to capacitive coupling between traces in the redistribution layer.
    Type: Grant
    Filed: September 21, 1998
    Date of Patent: November 30, 1999
    Assignee: VLSI Technology, Inc.
    Inventors: Jayarama N. Shenoy, Paul Findley