Patents by Inventor Paul Fons
Paul Fons has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9224460Abstract: Recording and erasing of data in PRAM have hitherto been performed based on a change in physical characteristics caused by primary phase-transformation of a crystalline state and an amorphous state of a chalcogen compound including Te which serves as a recording material. Since, however, a recording thin film is formed of a polycrystal but not a single crystal, a variation in resistance values occurs and a change in volume caused upon phase-transition has placed a limit on the number of times of readout of the record. In one embodiment, the above problem is solved by preparing a solid memory having a superlattice structure with a thin film containing Sb and a thin film containing Te. The solid memory can realize the number of times of repeated recording and erasing of 1015.Type: GrantFiled: June 21, 2013Date of Patent: December 29, 2015Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Junji Tominaga, James Paul Fons, Alexander Kolobov
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Patent number: 9153315Abstract: Recording and erasing of data in PRAM have hitherto been performed based on a change in physical characteristics caused by primary phase-transformation of a crystalline state and an amorphous state of a chalcogen compound including Te which serves as a recording material. Since, however, a recording thin film is formed of a polycrystal but not a single crystal, a variation in resistance values occurs and a change in volume caused upon phase-transition has placed a limit on the number of times of readout of record. In one embodiment, the above problem is solved by preparing a solid memory having a superlattice structure of thin films including Ge and thin films including Sb. The solid memory can realize the number of times of repeated recording and erasing of 1015.Type: GrantFiled: June 21, 2013Date of Patent: October 6, 2015Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Junji Tominaga, James Paul Fons, Alexander Kolobov
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Patent number: 9129673Abstract: A solid-state memory that requires a lower current during recording and erasing data and can repeatedly rewrite data an increased number of times. In at least one example embodiment, the solid-state memory includes a recording layer that includes a laminated structure in which electric properties are changed in response to a phase separation. The laminated structure includes a film containing an Sb atom(s) and a film containing a Ge atom(s), which films constitute a superlattice structure. In the laminated structure, phase separation of the film containing the Sb atom and the film containing the Ge atom allows data to be recorded and erased efficiently.Type: GrantFiled: February 24, 2010Date of Patent: September 8, 2015Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Junji Tominaga, Paul Fons, Alexander Kolobov
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Publication number: 20130286725Abstract: Recording and erasing of data in PRAM have hitherto been performed based on a change in physical characteristics caused by primary phase-transformation of a crystalline state and an amorphous state of a chalcogen compound including Te which serves as a recording material. Since, however, a recording thin film is formed of a polycrystal but not a single crystal, a variation in resistance values occurs and a change in volume caused upon phase-transition has placed a limit on the number of times of readout of the record. In one embodiment, the above problem is solved by preparing a solid memory having a superlattice structure with a thin film containing Sb and a thin film containing Te. The solid memory can realize the number of times of repeated recording and erasing of 1015.Type: ApplicationFiled: June 21, 2013Publication date: October 31, 2013Inventors: Junji Tominaga, James Paul Fons, Alexander Kolobov
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Publication number: 20130279247Abstract: Recording and erasing of data in PRAM have hitherto been performed based on a change in physical characteristics caused by primary phase-transformation of a crystalline state and an amorphous state of a chalcogen compound including Te which serves as a recording material. Since, however, a recording thin film is formed of a polycrystal but not a single crystal, a variation in resistance values occurs and a change in volume caused upon phase-transition has placed a limit on the number of times of readout of record. In one embodiment, the above problem is solved by preparing a solid memory having a superlattice structure of thin films including Ge and thin films including Sb. The solid memory can realize the number of times of repeated recording and erasing of 1015.Type: ApplicationFiled: June 21, 2013Publication date: October 24, 2013Inventors: Junji TOMINAGA, James Paul FONS, Alexander KOLOBOV
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Patent number: 8530314Abstract: A method of at least one embodiment of the present invention of manufacturing a solid-state memory is a method of manufacturing a solid-state memory, the solid-state memory including a recording film whose electric characteristics are varied by phase transformation, the method including: forming the recording film by forming a laminate of two or more layers so that a superlattice structure is provided, each of the layers having a parent phase which shows solid-to-solid phase-transformation, the recording film being formed at a temperature not lower than a temperature highest among crystallization temperatures of the parent phases. It is thus possible to manufacture a solid-state memory which requires lower current for recording and erasing data and has a greater rewriting cycle number.Type: GrantFiled: September 28, 2009Date of Patent: September 10, 2013Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Junji Tominaga, Takayuki Shima, Alexander Kolobov, Paul Fons, Robert Simpson, Reiko Kondo
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Patent number: 8396335Abstract: A solid memory may include a recording layer including Ge, Sb and Te as major components. The recording layer may include a superlattice. The recording layer may include multi-layers each having a parent phase showing a phase transformation in solid-states, the phase transformation causing change in electrical property of the recording layer. The recording layer may include an Sb2Te3 layer that includes at least one period of a first lamination of a first Te-atomic layer, a first Sb-atomic layer, a second Te-atomic layer, a second Sb-atomic layer, and a third Te-atomic layer in these order, a GeTe layer that includes at least one period of a second lamination of a fourth Te-atomic layer and a Ge-atomic layer, and an Sb layer that includes a plurality of Sb-atomic layers.Type: GrantFiled: January 20, 2010Date of Patent: March 12, 2013Assignee: Elpida Memory, Inc.Inventors: Junji Tominaga, Takayuki Shima, Alexander Kolobov, Paul Fons, Robert Simpson
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Patent number: 8335106Abstract: To include a superlattice laminate having laminated thereon a first crystal layer of which crystal lattice is a cubic crystal and in which positions of constituent atoms are reversibly replaced by application of energy, and a second crystal layer having a composition different from that of the first crystal layer, and an orientation layer that is an underlaying layer of the superlattice laminate and causes a laminated surface of the first crystal layer to be (111)-orientated. According to the present invention, the laminated surface of the first crystal layer can be (111)-orientated by using the orientation layer as an underlaying layer. In the first crystal layer of which laminated surface is (111)-orientated, a crystal structure reversibly changes when a relatively low energy is applied. Therefore, characteristics of a superlattice device having this crystal layer can be enhanced.Type: GrantFiled: May 3, 2010Date of Patent: December 18, 2012Assignee: Elpida Memory, Inc.Inventors: Kazuo Aizawa, Isamu Asano, Junji Tominaga, Alexander Kolobov, Paul Fons, Robert Simpson
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Patent number: 8295080Abstract: A solid-state memory device includes: a superlattice laminate having plural crystal layers laminated therein, the crystal layers including first and second crystal layers having mutually opposite compositions; a lower electrode provided on a first surface in a laminating direction of the superlattice laminate; and an upper electrode provided on a second surface of the superlattice laminate in the laminating direction. The first crystal layer included in the superlattice laminate is made of a phase change compound. According to the present invention, the superlattice laminate laminated in opposite directions of the upper and lower electrodes is sandwiched between these electrodes. Therefore, when an electric energy is applied to the superlattice laminate via these electrodes, a uniform electric energy can be applied to a laminated surface of the superlattice laminate. Accordingly, fluctuation of a resistance is small even when information is repeatedly rewritten, and data can be read stably as a result.Type: GrantFiled: June 4, 2010Date of Patent: October 23, 2012Assignee: Elpida Memory, Inc.Inventors: Kazuo Aizawa, Isamu Asano, Junji Tominaga, Alexander Kolobov, Paul Fons, Robert Simpson
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Patent number: 8097323Abstract: An object of the invention is to write-once record and reproduce, or only reproduce, a mark smaller than the resolution limit; obtain a high level of reproduction performance (CNR and the like); and realize a high level of reproduction durability. In the invention, between a signal reproducing functional layer composed of Sb or Te and a protecting layer there is introduced a thermally stable diffusion preventing layer, and thereby reactions between the signal reproducing functional layer and the protecting layer due to increased temperature can be prevented or suppressed while increasing reproduction durability.Type: GrantFiled: August 17, 2007Date of Patent: January 17, 2012Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Takayuki Shima, Yuzo Yamakawa, James Paul Fons, Junji Tominaga
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Publication number: 20110315942Abstract: A solid-state memory that requires a lower current during recording and erasing data and can repeatedly rewrite data an increased number of times. In at least one example embodiment, the solid-state memory includes a recording layer that includes a laminated structure in which electric properties are changed in response to a phase separation. The laminated structure includes a film containing an Sb atom(s) and a film containing a Ge atom(s), which films constitute a superlattice structure. In the laminated structure, phase separation of the film containing the Sb atom and the film containing the Ge atom allows data to be recorded and erased efficiently.Type: ApplicationFiled: February 24, 2010Publication date: December 29, 2011Applicant: National Institute of Advanced Industrial Science and TechnologyyInventors: Junji Tominaga, Paul Fons, Alexander Kolobov
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Publication number: 20110207284Abstract: A method of at least one embodiment of the present invention of manufacturing a solid-state memory is a method of manufacturing a solid-state memory, the solid-state memory including a recording film whose electric characteristics are varied by phase transformation, the method including: forming the recording film by forming a laminate of two or more layers so that a superlattice structure is provided, each of the layers having a parent phase which shows solid-to-solid phase-transformation, the recording film being formed at a temperature not lower than a temperature highest among crystallization temperatures of the parent phases. It is thus possible to manufacture a solid-state memory which requires lower current for recording and erasing data and has a greater rewriting cycle number.Type: ApplicationFiled: September 28, 2009Publication date: August 25, 2011Applicant: National Institute of Advanced Industrial Science and TechnologyInventors: Junji Tominaga, Takayuki Shima, Alexander Kolobov, Paul Fons, Robert Simpson, Reiko Kondo
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Publication number: 20100315867Abstract: A solid-state memory device includes: a superlattice laminate having plural crystal layers laminated therein, the crystal layers including first and second crystal layers having mutually opposite compositions; a lower electrode provided on a first surface in a laminating direction of the superlattice laminate; and an upper electrode provided on a second surface of the superlattice laminate in the laminating direction. The first crystal layer included in the superlattice laminate is made of a phase change compound. According to the present invention, the superlattice laminate laminated in opposite directions of the upper and lower electrodes is sandwiched between these electrodes. Therefore, when an electric energy is applied to the superlattice laminate via these electrodes, a uniform electric energy can be applied to a laminated surface of the superlattice laminate. Accordingly, fluctuation of a resistance is small even when information is repeatedly rewritten, and data can be read stably as a result.Type: ApplicationFiled: June 4, 2010Publication date: December 16, 2010Applicant: ELPIDA MEMORY, INCInventors: Kazuo AIZAWA, Isamu ASANO, Junji TOMINAGA, Alexander KOLOBOV, Paul FONS, Robert SIMPSON
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Publication number: 20100284218Abstract: To include a superlattice laminate having laminated thereon a first crystal layer of which crystal lattice is a cubic crystal and in which positions of constituent atoms are reversibly replaced by application of energy, and a second crystal layer having a composition different from that of the first crystal layer, and an orientation layer that is an underlaying layer of the superlattice laminate and causes a laminated surface of the first crystal layer to be (111)-orientated. According to the present invention, the laminated surface of the first crystal layer can be (111)-orientated by using the orientation layer as an underlaying layer. In the first crystal layer of which laminated surface is (111)-orientated, a crystal structure reversibly changes when a relatively low energy is applied. Therefore, characteristics of a superlattice device having this crystal layer can be enhanced.Type: ApplicationFiled: May 3, 2010Publication date: November 11, 2010Applicant: Elpida Memory, Inc.Inventors: Kazuo AIZAWA, Isamu Asano, Junji Tominaga, Alexander Kolobov, Paul Fons, Robert Simpson
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Publication number: 20100207090Abstract: In one embodiment of the present invention, recording and erasing of data in PRAM have hitherto been performed based on a change in physical characteristics caused by primary phase-transformation of a crystalline state and an amorphous state of a chalcogen compound including Te which serves as a recording material. Since, however, a recording thin film is formed of a polycrystal but not a single crystal, a variation in resistance values occurs and a change in volume caused upon phase-transition has placed a limit on the number of times of readout of the record. The above problem is solved by preparing a solid memory having a superlattice structure with a thin film containing Sb and a thin film containing Te. The solid memory can realize the number of times of repeated recording and erasing of 1015.Type: ApplicationFiled: June 13, 2008Publication date: August 19, 2010Inventors: Junji Tominaga, James Paul Fons, Alexander Kolobov
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Publication number: 20100200828Abstract: In one embodiment of the present invention, recording and erasing of data in PRAM have hitherto been performed based on a change in physical characteristics caused by primary phase-transformation of a crystalline state and an amorphous state of a chalcogen compound including Te which serves as a recording material. Since, however, a recording thin film is formed of a polycrystal but not a single crystal, a variation in resistance values occurs and a change in volume caused upon phase-transition has placed a limit on the number of times of readout of record. In one embodiment, the above problem is solved by preparing a solid memory having a superlattice structure of thin films including Ge and thin films including Sb. The solid memory can realize the number of times of repeated recording and erasing of 1015.Type: ApplicationFiled: June 13, 2008Publication date: August 12, 2010Inventors: Junji Tominaga, James Paul Fons, Alexander Kolobov
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Publication number: 20100181548Abstract: A solid memory may include a recording layer including Ge, Sb and Te as major components. The recording layer may include a superlattice. The recording layer may include multi-layers each having a parent phase showing a phase transformation in solid-states, the phase transformation causing change in electrical property of the recording layer. The recording layer may include an Sb2Te3 layer that includes at least one period of a first lamination of a first Te-atomic layer, a first Sb-atomic layer, a second Te-atomic layer, a second Sb-atomic layer, and a third Te-atomic layer in these order, a GeTe layer that includes at least one period of a second lamination of a fourth Te-atomic layer and a Ge-atomic layer, and an Sb layer that includes a plurality of Sb-atomic layers.Type: ApplicationFiled: January 20, 2010Publication date: July 22, 2010Applicant: Elpida Memory, Inc.Inventors: Junji Tominaga, Takayuki Shima, Alexander Kolobov, Paul Fons, Robert Simpson
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Publication number: 20100006815Abstract: A recording material for a phase change solid memory may include a uniform-mixed phase that includes: at least one of a Te-containing alkali metal iodide phase and a Te-containing silver iodide phase, and an Sb—Te alloy phase. The recording material shows at least one of a phase change and a phase separation which changes at least one of optical property and electrical property of the recording material.Type: ApplicationFiled: July 7, 2009Publication date: January 14, 2010Applicant: Elpida Memory, Inc.Inventors: Jyunji TOMINAGA, Paul FONS, Alexander V. KOLOBOV
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Publication number: 20090269542Abstract: An object of the invention is to write-once record and reproduce, or only reproduce, a mark smaller than the resolution limit; obtain a high level of reproduction performance (CNR and the like); and realize a high level of reproduction durability. In the invention, between a signal reproducing functional layer composed of Sb or Te and a protecting layer there is introduced a thermally stable diffusion preventing layer, and thereby reactions between the signal reproducing functional layer and the protecting layer due to increased temperature can be prevented or suppressed while increasing reproduction durability.Type: ApplicationFiled: August 17, 2007Publication date: October 29, 2009Inventors: Takayuki Shima, Yuzo Yamakawa, James Paul Fons, Junji Tominaga
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Patent number: 7605012Abstract: A light emitting device includes a silicon substrate (1), a silicon nitride film (2) formed on the surface of the silicon substrate (1), at least an n-type layer (3), (4) and a p-type layer (6), (7) which are formed on the silicon nitride film (2) and also which are made of a ZnO based compound semiconductor, and a semiconductor layer lamination (11) in which layers are laminated to form a light emitting layer. Preferably this silicon nitride film (2) is formed by thermal treatment conducted in an atmosphere containing nitrogen such as an ammonium gas. Also, in another embodiment, a light emitting device is formed by growing a ZnO based compound semiconductor layer on a main face of a sapphire substrate, the main face being perpendicular to the C-face thereof. As a result, it is possible to obtain a device using a ZnO based compound with high properties such as an LED very excellent in crystallinity and having a high light emitting efficiency.Type: GrantFiled: June 27, 2005Date of Patent: October 20, 2009Assignees: National Institute of Advanced Industrial Science & Tech., Rohm Co., Ltd.Inventors: Shigeru Niki, Paul Fons, Kakuya Iwata, Tetsuhiro Tanabe, Hidemi Takasu, Ken Nakahara