Abstract: A charge pump circuit for generating a negative voltage has a switched capacitor voltage inverter circuit arranged to receive at least one clock signal and generate a negative voltage therefrom; a regulation control loop providing a feedback path from the output of the switched capacitor voltage inverter circuit to a supply input of the switched capacitor voltage inverter circuit, wherein the regulation control loop has a filter arranged to filter the generated negative voltage; and an output arranged to output the filtered generated negative voltage.

Abstract: A charge pump circuit for generating a negative voltage has a switched capacitor voltage inverter circuit arranged to receive at least one clock signal and generate a negative voltage therefrom; a regulation control loop providing a feedback path from the output of the switched capacitor voltage inverter circuit to a supply input of the switched capacitor voltage inverter circuit, wherein the regulation control loop has a filter arranged to filter the generated negative voltage; and an output arranged to output the filtered generated negative voltage.

Abstract: A charge pump circuit for generating a negative voltage has a switched capacitor voltage inverter circuit arranged to receive at least one clock signal and generate a negative voltage therefrom; a regulation control loop providing a feedback path from the output of the switched capacitor voltage inverter circuit to a supply input of the switched capacitor voltage inverter circuit, wherein the regulation control loop has a filter arranged to filter the generated negative voltage; and an output arranged to output the filtered generated negative voltage.

Abstract: A charge pump circuit for generating a negative voltage has: a clock generator arranged to output at least one clock signal; a switched capacitor voltage inverter circuit including capacitive elements wherein the switched capacitor voltage inverter circuit receives the at least one clock signal and generates a negative voltage therefrom. The charge pump circuit further has a regulation control loop providing a feedback path from an output of the switched capacitor voltage inverter circuit to a supply input of the switched capacitor voltage inverter circuit, and an output arranged to output a generated negative voltage. The feedback path has an operational amplifier configured to generate a maximum charging supply voltage from a fed back level-shifted negative voltage and apply the maximum charging supply voltage to the input supply of the switched capacitor voltage inverter to charge at least one of the capacitive elements during a loop start up.

Abstract: A charge pump circuit for generating a negative voltage has a switched capacitor voltage inverter circuit arranged to receive at least one clock signal and generate a negative voltage therefrom; a regulation control loop providing a feedback path from the output of the switched capacitor voltage inverter circuit to a supply input of the switched capacitor voltage inverter circuit, wherein the regulation control loop has a filter arranged to filter the generated negative voltage; and an output arranged to output the filtered generated negative voltage.

Abstract: A charge pump circuit for generating a negative voltage has: a clock generator arranged to output at least one clock signal; a switched capacitor voltage inverter circuit including capacitive elements wherein the switched capacitor voltage inverter circuit receives the at least one clock signal and generates a negative voltage therefrom. The charge pump circuit further has a regulation control loop providing a feedback path from an output of the switched capacitor voltage inverter circuit to a supply input of the switched capacitor voltage inverter circuit, and an output arranged to output a generated negative voltage. The feedback path has an operational amplifier configured to generate a maximum charging supply voltage from a fed back level-shifted negative voltage and apply the maximum charging supply voltage to the input supply of the switched capacitor voltage inverter to charge at least one of the capacitive elements during a loop start up.

Abstract: An integrated circuit comprises a radio frequency (RF) power amplifier (PA) output stage; at least one amplifier stage prior to the RF PA output stage; a linear amplifier comprising a voltage feedback wherein the linear amplifier is operably coupled to a low frequency supply module such that the linear amplifier and low frequency supply module provide a combined first power supply to the RF PA output stage; and a switched mode power supply module arranged to provide a second power supply to the linear amplifier and to the at least one amplifier stage prior to the RF PA output stage.

Abstract: An integrated circuit comprises a radio frequency (RF) power amplifier (PA) output stage; at least one amplifier stage prior to the RF PA output stage; a linear amplifier comprising a voltage feedback wherein the linear amplifier is operably coupled to a low frequency supply module such that the linear amplifier and low frequency supply module provide a combined first power supply to the RF PA output stage; and a switched mode power supply module arranged to provide a second power supply to the linear amplifier and to the at least one amplifier stage prior to the RF PA output stage.

Abstract: A signal processing circuit has a first circuit, a digital-to-analog converter (DAC) and a second circuit. The first circuit receives a digital input signal with a non-zero direct current (DC) component, and subtracts at least a portion of the DC) component of the received digital input signal from the received digital input signal. The DAC is operably coupled to the first circuit, and arranged to perform a digital-to-analog conversion upon an output of the first circuit. The second circuit is operably coupled to the DAC, and arranged to add a DC component to an analog output signal derived from an output of the DAC. The signal processing circuit may be part of an integrated circuit or a wireless communication unit.

Abstract: An integrated circuit is described for providing a power supply to a radio frequency (RF) power amplifier (PA). The integrated circuit includes a low-frequency power supply path including a switching regulator and a high-frequency power supply path arranged to regulate an output voltage of a combined power supply at an output port of the integrated circuit for coupling to a load. The combined power supply is provided by the low-frequency power supply path and high-frequency power supply path. The high-frequency power supply path includes: an amplifier including a voltage feedback and arranged to drive a power supply signal on the high-frequency power supply path; and a capacitor operably coupled to the output of the amplifier and arranged to perform dc level shifting of the power supply signal.

Abstract: A signal processing circuit has a first circuit, a digital-to-analog converter (DAC) and a second circuit. The first circuit receives a digital input signal with a non-zero direct current (DC) component, and subtracts at least a portion of the DC) component of the received digital input signal from the received digital input signal. The DAC is operably coupled to the first circuit, and arranged to perform a digital-to-analog conversion upon an output of the first circuit. The second circuit is operably coupled to the DAC, and arranged to add a DC component to an analog output signal derived from an output of the DAC. The signal processing circuit may be part of an integrated circuit or a wireless communication unit.

Abstract: An integrated circuit for providing a differential interface for an envelope tracking signal is described. The integrated circuit includes a subtraction module having a first input for receiving a digital envelope tracking signal and a second input for receiving a second signal, wherein the subtraction module is arranged to subtract the second signal from the digital envelope tracking signal and produce an envelope tracking signal with a reduced average direct current (DC) component; a digital-to-analog converter (DAC) arranged to receive the envelope tracking signal with the reduced average DC component and produce a differential analog version thereof; and a modulator operably coupled to a differential output of the DAC, wherein the modulator comprises a DC input point arranged to insert a DC component into the differential analog version of the envelope tracking signal.

Abstract: An integrated circuit for providing a differential interface for an envelope tracking signal is described. The integrated circuit includes a subtraction module having a first input for receiving a digital envelope tracking signal and a second input for receiving a second signal, wherein the subtraction module is arranged to subtract the second signal from the digital envelope tracking signal and produce an envelope tracking signal with a reduced average direct current (DC) component; a digital-to-analog converter (DAC) arranged to receive the envelope tracking signal with the reduced average DC component and produce a differential analog version thereof; and a modulator operably coupled to a differential output of the DAC, wherein the modulator comprises a DC input point arranged to insert a DC component into the differential analog version of the envelope tracking signal.

Abstract: An integrated circuit is described for providing a power supply to a radio frequency (RF) power amplifier (PA). The integrated circuit includes a low-frequency power supply path including a switching regulator and a high-frequency power supply path arranged to regulate an output voltage of a combined power supply at an output port of the integrated circuit for coupling to a load. The combined power supply is provided by the low-frequency power supply path and high-frequency power supply path. The high-frequency power supply path includes: an amplifier including a voltage feedback and arranged to drive a power supply signal on the high-frequency power supply path; and a capacitor operably coupled to the output of the amplifier and arranged to perform dc level shifting of the power supply signal.

Abstract: A frequency agile voltage controlled oscillator is provided in which amplitude control is performed by digitally controlling the current supplied to the oscillator from a current source (10). The use of digital control means that phase noise performance of the oscillator is not degraded by the introduction of noise from the current source controller.

Abstract: A frequency agile voltage controlled oscillator is provided in which amplitude control is performed by digitally controlling the current supplied to the oscillator from a current source (10). The use of digital control means that phase noise performance of the oscillator is not degraded by the introduction of noise from the current source controller.

Abstract: Capacitor voltage coefficient errors are reduced in a lossy integrator by providing oppositely oriented first and second feedback capacitors in a switched capacitor feedback circuit coupled between the output and a summing conductor connected to an inverting input of an operational amplifier. During a first clock signal, terminals of the first feedback capacitor are coupled to a reference voltage by closing first and second reset switches and the second feedback capacitor is coupled between the inverting input and the output conductor by closing first and second sampling switches. Then, during a second clock signal the terminals of the second feedback capacitor are coupled to the first reference voltage by closing third and fourth reset switches, and the second feedback capacitor is coupled between the inverting input and the output by closing third and fourth sampling switches.

Abstract: A self-calibrating digital-to-analog converter includes a delta-sigma modulator (25) receiving a digital input signal, an output producing a stream of digital pulses the density of which represents a value of the digital input signal, and an intermediate digital input port coupled to a digital summing element which is also coupled to an output of an integrator within the delta-sigma modulator. A 1-bit DAC converts the stream of digital pulses to an analog signal that is filtered to produce an analog output voltage. A 1-bit DAC converts the analog output signal to a digital feedback signal, and a successive approximation circuit produces a digital offset correction signal from the digital feedback signal and loads it into an offset register. An output port of the offset register is coupled to the intermediate digital input port to provide self-calibration of an offset error without skewing an input range of the digital input signal.