Abstract: A suspension training device, system and method for using the same is disclosed. A suspension training device includes an elongated strap, a handle at a first end of the elongated strap, a harness at a second end of the elongated strap, and one or more stops, each stop being affixed at a position along a length of the elongated strap between the handle and the harness. A gravity training system includes two or more suspension training devices. The suspension training devices can be suspending with a stationary object by the stops, such as the elongated strap being threaded between a door and a doorframe, to a desired length to allow a user to accomplish any number of exercises or gravity-resistant movement.

Abstract: A suspension training device, system and method for using the same is disclosed. A suspension training device includes an elongated strap, a handle at a first end of the elongated strap, a harness at a second end of the elongated strap, and one or more stops, each stop being affixed at a position along a length of the elongated strap between the handle and the harness. A gravity training system includes two or more suspension training devices. The suspension training devices can be suspending with a stationary object by the stops, such as the elongated strap being threaded between a door and a doorframe, to a desired length to allow a user to accomplish any number of exercises or gravity-resistant movement.

Abstract: A suspension training device, system and method for using the same is disclosed. A suspension training device includes an elongated strap, a handle at a first end of the elongated strap, a harness at a second end of the elongated strap, and one or more stops, each stop being affixed at a position along a length of the elongated strap between the handle and the harness. A gravity training system includes two or more suspension training devices. The suspension training devices can be suspending with a stationary object by the stops, such as the elongated strap being threaded between a door and a doorframe, to a desired length to allow a user to accomplish any number of exercises or gravity-resistant movement.

Abstract: Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.

Abstract: For an integrated circuit (IC) that retrieves data from a memory device external to the IC, a novel memory interface module that generates a sampling clock to the memory device and samples the retrieved data is described. The memory interface module adjusts the frequency of the sampling clock and selects a sampling time for sampling the retrieved data. The memory interface includes a training module that monitors a data pin of the memory device for transitions. The training module searches and records the earliest transition and the latest transition with respect to the period of the sampling clock. The memory interface module uses the earliest transition and the latest transition to determine an interval of data uncertainty (uncertainty interval) for the data pin. The memory interface module facilitates determining a new sampling time and a new sampling clock frequency based on the uncertainty intervals.

Abstract: An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.

Abstract: A method for storing data in a memory chip that includes a memory core having dynamic random access memory cells, is performed by a memory controller chip. The method includes sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation. After sending the write command, the memory controller chip waits for a first time period corresponding to a time period during which the write command is stored by the memory chip, and sends data associated with the write operation to a second interface of the memory chip, wherein the sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period.

Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes tuning circuitry within the slave device such that the performance of the memory system is improved.

Abstract: Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.

Abstract: A method for storing data in a memory chip that includes a memory core having dynamic random access memory cells, is performed by a memory controller chip. The method includes sending a write command to a first interface of the memory chip, wherein the write command specifies a write operation. After sending the write command, the memory controller chip waits for a first time period corresponding to a time period during which the write command is stored by the memory chip, and sends data associated with the write operation to a second interface of the memory chip, wherein the sending of the data occurs after a second time period transpires, the second time period following the first time period, such that sending the write command and sending the data are separated by a first predetermined delay time that includes both the first time period and the second time period.

Abstract: An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit to the DRAM a first code to indicate that first data is to be written to the DRAM. The first code is to be sampled by the DRAM and held by the DRAM for a first period of time before it is issued inside the DRAM. The interface is further to transmit the first data that is to be sampled by the DRAM after a second period of time has elapsed from when the first code is sampled by the DRAM. The interface is further to transmit a second code, different from the first code, to indicate that second data is to be read from the DRAM. The second code is to be sampled by the DRAM on one or more edges of the external clock signal.

Abstract: An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit, over a first plurality of wires, to the DRAM a first code to indicate that first data is to be written to the DRAM and a column address to indicate a column location of a memory core in the DRAM where the first data is to be written. The interface is further to transmit a second code to indicate whether mask information for the first data will be sent to the DRAM. If the second code indicates that mask information will be sent, a portion of the column address and a portion of the mask information are sent after the second code is sent. The interface is further to transmit to the DRAM, over a second plurality of wires separate from the first plurality of wires, the first data.

Abstract: A memory controller has an interface to convey, over a first set of interconnect resources: a first command that specifies activation of a row of memory cells, a second command that specifies a write operation directed to the row of memory cells, a bit that specifies whether precharging will occur in connection with the write operation, a code that specifies whether data mask information will be issued in connection with the write operation, and if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation. The memory controller interface further conveys, over a second set of interconnect resources, separate from the first set of interconnect resource, the write data.

Abstract: A memory component includes a memory core, a control transport block to receive a write command from external control lines, and a write control buffer to store the write command for a first time period after the write command is received at the transport block. A data buffer receives data from external data lines, the data to be stored in the memory core in response to the write command, wherein receipt of the data occurs based on a second time period that follows the first time period, such that receipt of the write command and the data are separated by a delay time that includes both the first time period and the second time period. A write mask buffer receives write masking information from an external write mask line. Receipt of the write command and the write masking information are separated by the delay time.

Abstract: Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.

Abstract: A memory controller has an interface to convey, over a first set of interconnect resources: a first command that specifies activation of a row of memory cells, a second command that specifies a write operation directed to the row of memory cells, a bit that specifies whether precharging will occur in connection with the write operation, a code that specifies whether data mask information will be issued in connection with the write operation, and if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation. The memory controller interface further conveys, over a second set of interconnect resources, separate from the first set of interconnect resource, the write data.

Abstract: In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.

Abstract: A suspension training device, system and method for using the same is disclosed. A suspension training device includes an elongated strap, a handle at a first end of the elongated strap, a harness at a second end of the elongated strap, and one or more stops, each stop being affixed at a position along a length of the elongated strap between the handle and the harness. A gravity training system includes two or more suspension training devices. The suspension training devices can be suspending with a stationary object by the stops, such as the elongated strap being threaded between a door and a doorframe, to a desired length to allow a user to accomplish any number of exercises or gravity-resistant movement.

Abstract: A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the first time period, the write operation is initiated in response to the write command. During the write operation, unmasked portions of received data are written to the memory core, where the unmasked portions of the data are bits of the data that are identified by received mask information as not being masked.