Abstract: Computing systems with dynamic architectures may be used to secure against code-injection attacks and other exploits. A system may generate multiple representations of instructions or other data associated with each of a set of configurations of the system. The system may periodically or randomly change configurations such that malicious code that is executable in one configuration cannot be executed in another configuration. A system may also detect malicious code by comparing code previously generated in one representation with different representations of the same code. If, during execution of a representation of a program code, the system determines that the representation specifies instructions that differ from other representations of the same program code, they system may stop executing the compromised program code, change its configuration, and continue to execute another representation of the program code that has not been compromised.

Abstract: Implementations of a method of detecting a plurality of radio pulses may include, using a signal processor, combining at least three pulses included in radio data collected over a first time interval by a directional antenna coupled with a software defined radio coupled with a unmanned aerial vehicle (UAV), the UAV coupled with a base station including the signal processor; determining a detected time for each of the at least three pulses in the first time interval; using the detected time for each of the at least three pulses, predicting a future time for each of at least three future pulses; and, using the software defined radio and directional antenna, listening for each of the at least three future pulses in radio data over a second time interval.

Abstract: A system includes a memory device configured to store data at addressable locations in the memory device, a physically unclonable function (PUF) device including an array of PUF elements, and a memory interface coupled to the memory device and the PUF device. The memory interface is configured to receive a request to store first data in the memory device, store the first data in the memory device at a first location of the memory device, and transmit the first data and the first location to the PUF device. The PUF device is configured to create a first challenge value using the first data and the first location, generate a first response value using the first challenge value, and store the first response value as a first data integrity tag in the memory device, wherein the first data integrity tag is associated with the first data.

Abstract: Disclosed herein is a computing system with the capability to execute instructions in different positional notation values. The definition of a positional notation value is given by the general formula that represent a base 10 numeral in any positional notation in the following manner: . . . d3r3+d2r2+d1r1+d0r0, where d is a coefficient, r is the base of the positional number system (i.e. r=2 for binary, or r=3 for ternary), and the exponent is the position of the digit. The computing may provide a configuration which hybridizes the instructions of multiple positional notation values in variable ratios. The computing system may dynamically switch between the multiple hybridized instructions sets. Embodiments may be applied to provide security benefits.

Abstract: A system includes a memory device configured to store data at addressable locations in the memory device, a physically unclonable function (PUF) device including an array of PUF elements, and a memory interface coupled to the memory device and the PUF device. The memory interface is configured to receive a request to store first data in the memory device, store the first data in the memory device at a first location of the memory device, and transmit the first data and the first location to the PUF device. The PUF device is configured to create a first challenge value using the first data and the first location, generate a first response value using the first challenge value, and store the first response value as a first data integrity tag in the memory device, wherein the first data integrity tag is associated with the first data.

Abstract: Computing systems with dynamic architectures may be used to secure against code-injection attacks and other exploits. A system may generate multiple representations of instructions or other data associated with each of a set of configurations of the system. The system may periodically or randomly change configurations such that malicious code that is executable in one configuration cannot be executed in another configuration. A system may also detect malicious code by comparing code previously generated in one representation with different representations of the same code. If, during execution of a representation of a program code, the system determines that the representation specifies instructions that differ from other representations of the same program code, they system may stop executing the compromised program code, change its configuration, and continue to execute another representation of the program code that has not been compromised.

Abstract: Disclosed herein is a computing system with the capability to execute instructions in different positional notation values. The definition of a positional notation value is given by the general formula that represent a base 10 numeral in any positional notation in the following manner: . . . d3r3+d2r2+d1r1+d0r0, where d is a coefficient, r is the base of the positional number system (i.e. r=2 for binary, or r=3 for ternary), and the exponent is the position of the digit. The computing may provide a configuration which hybridizes the instructions of multiple positional notation values in variable ratios. The computing system may dynamically switch between the multiple hybridized instructions sets. Embodiments may be applied to provide security benefits.

Abstract: Disclosed herein is a computing system with the capability to execute instructions in different positional notation values. The definition of a positional notation value is given by the general formula that represent a base 10 numeral in any positional notation in the following manner: . . . d3r3+d2r2+d1r1+d0r0, where d is a coefficient, r is the base of the positional number system (i.e. r=2 for binary, or r=3 for ternary), and the exponent is the position of the digit. The computing may provide a configuration which hybridizes the instructions of multiple positional notation values in variable ratios. The computing system may dynamically switch between the multiple hybridized instructions sets. Embodiments may be applied to provide security benefits.

Abstract: Systems and methods for prioritizing executions of a plurality of instructions in a computer system (such as an embedded system) are disclosed. An instruction can be associated with a priority and an atomicity. When an instruction is fetched, the computer system can access the priority and atomicity information together with the accessing the operand and decoding the instruction. The instruction may be executed in accordance with the fetched priority and atomicity. In some situations, the plurality of instructions may be executed in parallel by multiple functional units. Some of the functional units may be the same type, and therefore allowing multiple instructions to use the same type of functional unit at the same time, without waiting for another instruction to finish.

Abstract: Disclosed herein is a computing system with the capability to execute instructions in different positional notation values. The definition of a positional notation value is given by the general formula that represent a base 10 numeral in any positional notation in the following manner: . . . d3r3+d2r2+d1r1+d0r0, where d is a coefficient, r is the base of the positional number system (i.e. r=2 for binary, or r=3 for ternary), and the exponent is the position of the digit. The computing may provide a configuration which hybridizes the instructions of multiple positional notation values in variable ratios. The computing system may dynamically switch between the multiple hybridized instructions sets. Embodiments may be applied to provide security benefits.

Abstract: Implementations of UAV wildlife monitoring system may include a ground control station wirelessly coupled to a UAV which may include a flight controller, a first radio, a second radio, a first antenna, a second antenna, a very high frequency (VHF) radio receiver, and a computer, all operatively coupled together. The monitoring system may also include a VHF tag configured to be coupled to an animal, wherein when the VHF tag is coupled to the animal, the VHF radio receiver receives a VHF radio signal from the VHF tag using the first antenna, wherein the computer process the VHF radio signal to create the location data from the VHF radio signal, processes the location data, and sends the location data to the second radio, wherein the second radio transmits the location data into a telecommunications channel, and wherein the ground control station receives the location data from the telecommunications channel.

Abstract: A system for optimizing energy efficiency of an embedded system. A hardware abstraction layer (HAL) is coupled to hardware of an embedded system. An energy hardware abstraction layer (eHAL) couples to the hardware and to the HAL. A hypervisor couples to the HAL and to the eHAL. One or more applications couple to the hypervisor, the HAL and the eHAL. The eHAL measures energy use of the embedded system, constructs a model of energy use of the embedded system and, using the model, determines how to one of reduce and minimize energy use of the embedded system. The hypervisor is configured to alter one or more hardware parameters to one of reduce and minimize energy use of the embedded system as the embedded system performs one or more tasks. In implementations a real time operating system (RTOS) is coupled to the one or more applications and to the hypervisor.

Abstract: Systems and methods for prioritizing executions of a plurality of instructions in a computer system (such as an embedded system) are disclosed. An instruction can be associated with a priority and an atomicity. When an instruction is fetched, the computer system can access the priority and atomicity information together with the accessing the operand and decoding the instruction. The instruction may be executed in accordance with the fetched priority and atomicity. In some situations, the plurality of instructions may be executed in parallel by multiple functional units. Some of the functional units may be the same type, and therefore allowing multiple instructions to use the same type of functional unit at the same time, without waiting for another instruction to finish.

Abstract: Implementations of UAV wildlife monitoring system may include a ground control station wirelessly coupled to a UAV which may include a flight controller, a first radio, a second radio, a first antenna, a second antenna, a very high frequency (VHF) radio receiver, and a computer, all operatively coupled together. The monitoring system may also include a VHF tag configured to be coupled to an animal, wherein when the VHF tag is coupled to the animal, the VHF radio receiver receives a VHF radio signal from the VHF tag using the first antenna, wherein the computer process the VHF radio signal to create the location data from the VHF radio signal, processes the location data, and sends the location data to the second radio, wherein the second radio transmits the location data into a telecommunications channel, and wherein the ground control station receives the location data from the telecommunications channel.

Abstract: A system for optimizing energy efficiency of an embedded system. A hardware abstraction layer (HAL) is coupled to hardware of an embedded system. An energy hardware abstraction layer (eHAL) couples to the hardware and to the HAL. A hypervisor couples to the HAL and to the eHAL. One or more applications couple to the hypervisor, the HAL and the eHAL. The eHAL measures energy use of the embedded system, constructs a model of energy use of the embedded system and, using the model, determines how to one of reduce and minimize energy use of the embedded system. The hypervisor is configured to alter one or more hardware parameters to one of reduce and minimize energy use of the embedded system as the embedded system performs one or more tasks. In implementations a real time operating system (RTOS) is coupled to the one or more applications and to the hypervisor.