Patents by Inventor Paul G. G. VanLoon

Paul G. G. VanLoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CMOS structure and method utilizing retarded electric field for minimum latch-up
    Patent number: 4203126
    Abstract: CMOS device and method utilizing a retarded electric field for reducing the current gain in the base region of parasitic transistors in the device. A buried layer is utilized in the base region of the parasitic transistor, and the resistivities of the buried layer and substrate are chosen to reduce both NPN and PNP betas and also to reduce the distributed resistance shunting the P+N and N+P junctions, thereby increasing the level of current required to produce latch-up in the device.
    Type: Grant
    Filed: November 13, 1975
    Date of Patent: May 13, 1980
    Assignee: Siliconix, Inc.
    Inventors: Ernest W. Yim, Paul G. G. VanLoon
  • Method of making CMOS structure with retarded electric field for minimum latch-up
    Patent number: 4161417
    Abstract: Method for making CMOS device utilizing a retarded electric field for reducing the current gain in the base region of parasitic transistors in the device. A buried layer is utilized in the base region of the parasitic transistor, and the resistivities of the buried layer and substrate are chosen to reduce both NPN and PNP betas and also to reduce the distributed resistance shunting the P+N and N+P junctions, thereby increasing the level of current required to produce latch-up in the device.
    Type: Grant
    Filed: October 17, 1977
    Date of Patent: July 17, 1979
    Assignee: Siliconix Corporation
    Inventors: Ernest W. Yim, Paul G. G. VanLoon