Abstract: For the protection of an integrated circuit against ESD, it is known to use a Silicon-Controlled Rectifier (SCR), provided with a gated diode or MOS transistor at the periphery of the well to obtain a low trigger voltage. In accordance with the invention, the said gated diode or MOS transistor, located between the anode and the cathode of the SCR, is provided only along a part of the periphery of the SCR, a part of the SCR thus being free from the said gated diode. As a result of this structure, the holding voltage of the SCR is reduced considerably, leading to an important decrease of the dissipation during the ESD event.

Abstract: Method of manufacturing the quality of contacts e.g. in an LCD module in which an IC is so placed on the surface of a substrate that the external connections of the IC electrically contact the desired interconnections on the substrate. The quality of the electrical contacts is tested by powering up the IC and running a selftest program. This selftest checks all contacts between the external connections of the device and the interconnections on the substrate, e.g. the row-column conductors on the LCD-glass. Due to a possibly poor ohmic contact the signals from the driver-IC may be delayed, the delay measured being representative for the quality of the contact.

Abstract: The data processing circuit has a self-timed instruction execution unit, which operates asynchronously, signalling the completion of processes and starting subsequent processes in response to such signalling. In order to satisfy real time constraints upon program execution ready signals generated after completion of selected instructions are gated with a timer signal before they are used to start a next instruction. In an embodiment, the amount of time left between the ready signal is used to start a next instruction is measured and used to regulate a power supply voltage of the instruction execution unit so that it is just high enough to make the instruction execution unit sufficiently fast to meet the real time constraints.

Abstract: In the manufacture of integrated circuits, damage to transistors caused by ESD is customarily precluded by connecting the gates of the transistors, in an early stage, to a protection diode. If, for example during plasma etching or reactive ion etching, an electric charge is stored on a floating gate, this charge can be removed via the diode before electric breakdown occurs. In a first embodiment of a device in accordance with the invention, the diode is formed in an active region covered by an electrically insulating layer 12. The gate 8, or a poly track 9 connected thereto, projects above this layer and covers only a part of the active region. In the uncovered part of the active region, a cathode or anode is provided so as to be self-aligned relative to the poly track. In another embodiment, the poly track 9 is situated directly next to the region of the diode. The poly track 9 and the surface zone 10 of the protection diode are interconnected by an overlapping metal contact 15.