Abstract: A base station node is provided that includes a radio frequency (RF) monitor and at least one signal processor. The RF monitor is operable to monitor traffic associated with a plurality of wireless communication devices to determine at least one requested load having a corresponding air interface standard. The signal processor is coupled to the RF monitor and is operable to be dynamically reconfigured to support the air interface standard corresponding to the requested load.

Abstract: A repeater for re-transmitting an incoming RF signal comprising: a first antenna array for receiving the incoming RF signal; a second antenna array for transmitting an outgoing RF signal; and a transceiver for down-converting the incoming RF signal to a down-converted signal, processing the down-converted signal, and up-converting the processed signal to produce the outgoing RF signal. The first antenna array is cross-polarized with respect to the second antenna array. The repeater also comprises an echo processor for attenuating in the down-converted signal an echo signal associated with the outgoing RF signal. The echo processor delays transmission of the outgoing RF signal in order to minimize the echo signal.

Abstract: A repeater for re-transmitting signals between first and second wireless devices. The repeater comprises a first antenna array for receiving a forward channel signal transmitted from the first wireless device and a second antenna array for receiving a reverse channel signal transmitted from the second wireless device. The repeater also comprises a first transceiver chain for down-converting the received forward channel signal, processing the down-converted forward channel signal, and up-converting the processed forward channel signal to thereby produce an outgoing forward channel signal. The repeater also comprises a second transceiver chain for down-converting the received reverse channel signal, processing the down-converted reverse channel signal, and up-converting the processed reverse channel signal to thereby produce an outgoing reverse channel signal.

Abstract: There is disclosed an apparatus for resetting an asynchronous transfer mode (ATM) compatible system. The apparatus comprises a reset detection circuit coupled to an input port of the ATM compatible system that receives from the input port an incoming ATM bitstream. The reset detection circuit compares data in the incoming ATM bitstream to a first reset bit pattern and generates a first reset signal in response to a match between the data in the incoming ATM bitstream and the first reset bit pattern.

Abstract: The circuit comprises a serial to parallel converter for extracting the signalling bits from the various channels of the data streams and for providing a serial stream of signalling bits, and a read-write memory having a plurality of locations at least as large as the number of channels in the data streams, each location having at least the number of cells necessary to store a byte of signalling data and the signalling message header. The converter outputs the signalling bits from consecutive channels of the data streams into a one-byte shift register adapted to shift the bits laterally as well as receive and output a byte of data in parallel from and unto a bus connected to memory.