Abstract: The invention is, in its various aspects, an apparatus and a method for scanning a keypad or a keyboard. The apparatus comprises a keypad and an integrated circuit. The keypad includes a plurality of chained resistors and a plurality of key switches. Each of the plurality of key switches is tied to a common node at a first terminal thereof and tapping the chained resistors at a second node thereof. Each of the key switches generates a signal indicative of the respective key switch being pressed when the key switch is pressed. The integrated circuit is capable of receiving the generated signal. The integrated circuit furthermore includes an analog to digital converter capable of generating a reference signal and a circuit capable of determining which key switch has been pressed from the magnitude of the generated voltage signal and the reference signal.

Abstract: A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

Abstract: Described herein is a system and method of disabling D bits in a CT2 MUX signaling channel. When the bit count equals the bit location of where the D bits are typically located in the signaling channel of a CT2 MUX, circuitry of the present invention disables a D bit enable signal from being processed. The D bit enable signal would typically allow a transmitter and receiver to, respectively, send a bit as a D bit, or process a received bit as a D bit. The suffix of the CT2 MUX, consisting of D bits, is unaffected by the present invention.

Abstract: A phase detector using simple arithmetic operations to measure phase errors in the carrier-recovery mechanism for a DQPSK digital communications receiver. The carrier-recovery mechanism is a feedback loop that provides a synchronization between the oscillators in the transmitter and receiver of the communications system; the phase detector measures deviations from this synchronization and generates a phase-error signal used in the feedback loop to synchronize the oscillators. To perform this measurement, the phase detector takes the received signal as input and compares it against a local oscillator in the receiver to generate two digital signals: the in-phase (I) and quadrature-phase (Q) components of the received signal. These signals are the input to a logic unit, which uses these two signals to determine the phase-error signal.

Abstract: A carrier-recovery loop for a receiver in a communication system with features that facilitate initialization of the loop. The carrier-recovery loop is a PLL that uses a feedback signal to keep a recovery oscillator phase-locked to the carrier of a received signal. In the present invention, an initializing value of the feedback signal is stored in a memory and provided to a digitally controlled recovery oscillator (DCO). This initializing value brings the recovered signal to an initial frequency that approximates the carrier frequency. When the receivers starts to acquire a phase-lock with the carrier, the carrier-recovery loop is in a condition close to the desired phase lock. Preparing the DCO in this manner imparts a significant improvement to the carrier-recovery loop. The response time for the loop to acquire a phase lock depends in part on its initial frequency offset from the carrier. In general, reducing this initial offset reduces the loop's acquisition time.

Abstract: A system and method of muting a voice signal in a wireless communication system when an "all zeros" condition of a digitized serial voice input signal is detected. The mute signal which is generated when a zeros condition occurs is provided to a voice processor to initiate a mute algorithm to mute the processing of incoming voice data during the sample time of the zeros condition.

Abstract: A system and method is described herein for providing FDD and TDD modes of operation for a wireless communications device. The system includes a clock signal for FDD mode operation, a separate clock signal for TDD mode operation, where the TDD mode clock is twice the frequency of the FDD clock. Additionally, a counter is provided for counting bit times during a transmission or receive frame. The clock counter is reloaded after a pre-specified count is achieved. The pre-specified count is twice as great in TDD mode operation than in FDD mode operation to account for the fact that the bit periods are twice as long in FDD operation than during TDD operation since transmit and receive are at different frequencies and are not sharing the same channel.

Abstract: A programmable drive strength buffer includes a control signal used to enable/disable an output drive transistor slew rate control circuit, and a current drive strength control bits which are used to select weak, medium or strong current drive capability over an ISA bus with loads varying from 60 pF to 240 pF for a supply voltage of 5.0 or 3.3 volts.

Abstract: A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data.

Abstract: A supply voltage detect circuit is described which generates a control signal indicating the status of VCC to be at 5.0 or 3.3 volts. This control signal is used to generate analog reference signals used by A/D and/or D/A circuitry in an audio processing integrated circuit and by other circuitry to control clock frequencies or current drive.

Abstract: A supply voltage detect circuit is described which generates a control signal indicating the status of VCC to be at 5.0 or 3.3 volts. This control signal is used to generate analog reference signals used by A/D and/or D/A circuitry in an audio processing integrated circuit and by other circuitry to control clock frequencies or current drive.

Abstract: A clock switcher circuit for providing at least one set of clock signals selected from a plurality of clock sources. A first clock signal having a first pulse length and a second clock signal having a second pulse length are circuit inputs. Another circuit input is a clock selection input. When the clock selection input indicates a new output clock signal, different from the then current output clock signal, should be output by the circuit, the circuit provides a means for switching to output the new output clock signal. In switching to output the new output clock signal, the circuit prevents the occurrence of the output clock signal ever having a pulse shorter than the normal pulse length of the then current output clock signal, whether the then current output clock signal is the first clock signal or the second clock signal.

Abstract: An input buffer is described which is configurable depending on whether a 5.0 or 3.3 volt supply voltage is present, The input buffer includes two input buffer circuits. The output of a first input buffer circuit is output as valid data when the supply voltage VCC equals 5.0 volts. The output of the second input buffer circuit is output as valid data when the supply voltage VCC equals 3.3 volts.

Abstract: A cache organizational signal ("CORG signal") selects between cache organizations. A cache organization is chosen according to the speed of the main memory that is paired with the cache to handle different size blocks of instructions. When the CORG signal organizes the cache to handle blocks having few instructions per block, many blocks are present and a higher hit rate occurs, which works well with a fast main memory. When the CORG signal organizes the cache to handle blocks having more instructions per block, fewer blocks are present, a lower hit rate occurs, and processor idle cycles decrease, which works well with a slower main memory.

Abstract: A dynamic programmable logic array circuit includes an AND logic plane (12), an inter-plane buffer (22), and an OR logic plane (14). The inter-plane buffer (22) is formed of a plurality of N-channel inter-plane FETs. Each of the plurality of N-channel inter-plane FETs has its gate electrode connected to a respective one of a plurality of product term lines and its source electrode connected to a respective one of a plurality of OR plane input lines. The drain electrodes of the plurality of inter-plane FETs are connected to receive an OR plane evaluation signal.

Abstract: A CMOS D-type flip-flop circuit stage for avoiding the possibilty of feedthrough includes a non-overlapping clock generator section having a true clock output and a complement clock output. The flip-flop circuit includes a master section formed of a first transfer gate, a first regenerative transistor and a first inverter gate. The flip-flop circuit further includes a slave section formed of a second transfer gate, a second regenerative transistor and a second inverter gate. The clock generator provides a two-phase non-overlapping clock for clocking both the master and slave sections so as to prevent inadvertent racethrough of data input to successive stages.

Abstract: Twenty-five capacitive keyswitches 16a-e are arranged in a matrix having five row conductors 12a-e and five column conductors 14a-e. A series of five pulses are fed to each row conductor 14a-e in succession through AND gates 41a-e controlled by a counter 34. Each time a row conductor 12a-e is pulsed, all of the column conductors 14a-e are scanned. When one of the column conductors 14a-e is scanned, the associated coupling transistor 54a-e is turned on and the associated discharge transistor 50a-e is turned off. The remaining coupling transistor 54a-e of the remaining columns 14a-e are off and the remaining discharge transistors 50a-e are on.