Patents by Inventor Paul G. Snaphaan

Paul G. Snaphaan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5467371
    Abstract: Arrangement for generating pulse code modulation values in a telephone set, comprising a microprocessor which includes a working store, in which the microprocessor and the working store are connected by a data bus and an address bus, further including an output circuit for outputting the pulse code modulation values, an output memory connected thereto for storing the pulse code modulation values to be output, the working store and the output memory being incorporated in a single memory circuit. The arrangement is preferably structured in such a way that it comprises an addressing device for generating, in response to the microprocessor's addressing of a random location of the output memory, an address of an output memory location to be read out.
    Type: Grant
    Filed: September 24, 1992
    Date of Patent: November 14, 1995
    Assignee: U.S. Philips Corporation
    Inventors: Gijsbertus A. Van Koelen, Paul G. Snaphaan, Gertjan Rhebergen
  • Patent number: 5293409
    Abstract: Communication of digital information between digital systems (2, 3) comprising clock generators (8, 9) is effected via storage in memory locations a1 to a8 and b1 to b8 of a cyclic buffer 4, in which, in succession, the information is written and read on a time base determined by the various clock generators (8, 9). Pointers stored in pointers (12, 13) determine the memory locations to be read out or written. If the pointers have become equal as a result of phase deviations of the clock generators (8, 9), this is detected by an address distance monitoring means (14) and made unequal and set to a maximum difference value relative to each other. The difference value amounts to half the number of memory locations n in a row of the buffer 4. For full duplex transmission the buffer 4 preferably comprises a double row of memory locations a1-an and b1-bn respectively.
    Type: Grant
    Filed: November 7, 1991
    Date of Patent: March 8, 1994
    Assignee: U.S. Philips Corporation
    Inventors: Anthony Doornenbal, Paul G. Snaphaan