Abstract: Disclosed herein is sophisticated but low-cost debug hardware which may be used to identify the root cause of a functional or electrical problem in a microprocessor chip. The debug hardware provides for generating a hardware breakpoint trap (HBT) in response to programmed combinations of internal signal triggers, and if desired, a HBT may be delayed through one or more occurrences of a programmed trigger combination via use of an iteration counter. Apparatus for generating and handling a HBT may comprise one or more trigger means, one or more event generation means, and debug software comprising code for 1) preserving the current architected state of a microprocessor upon generation of a HBT, 2) vectoring to and initiating execution of trap handler code, and 3) restoring said preserved current architected state after said trap handler code has been executed.

Abstract: A system and method for extracting custom debug signals from an integrated circuit chip. The custom debug signals, which are normally extracted via bonded custom debug pads during the testing of the chip, are made available in production chips, where the custom debug pads are not bonded and therefore unavailable, via the external I/O bus of the integrated circuit. In a preferred embodiment, the integrated circuit operates normally to drive standard debug data from internal nodes of the integrated circuit onto the I/O bus during idles cycles in the normal operation of the integrated circuit. Selection means may be set to drive the custom debug signals onto the I/O bus during idle cycles of normal integrated circuit operation rather than the standard debug data.

Abstract: Disclosed herein is sophisticated but low-cost debug hardware which may be used to identify the root cause of a functional or electrical problem in a microprocessor chip. The debug system comprises a raw mode trigger capability which allows microprocessor events to be generated either synchronously or asynchronously to a clock which steps an instruction pipeline. The debug system comprises one or more trigger means, one or more event generation means, and programmable means for alternately placing the one or more trigger means in synchronous or asynchronous mode. Each of the trigger means is implemented internally to a microprocessor so as to sample microprocessor signals and generate a number of triggers as programmed values of the microprocessor signals are detected.

Abstract: Presented is test system for use in debugging functional and electrical failures of an integrated circuit. The test system includes a diagnostics retrieval system and a test access port retrieval system external to the integrated circuit under test, and a debug trigger apparatus and test access port within the integrated circuit under test. The programmable debug trigger apparatus which resides internal and integral to the integrated circuit generates a trigger capture signal within a programmed delay after a set of monitored integrated circuit signals matches a programmed trigger condition. The test access port of the integrated circuit monitors a plurality of test nodes located throughout the integrated circuit and latches a set of test node signals present on test nodes located throughout the integrated circuit when it receives a trigger capture signal from the debug trigger apparatus.

Abstract: Presented is an internal integrated debug trigger apparatus for use in debugging functional and electrical failures of an integrated circuit chip. The debug trigger apparatus includes a plurality of software programmable trigger registers and a plurality of software programmable trigger function blocks. Each trigger register monitors a plurality of integrated circuit signals which may include signals sent to the external pins of the integrated circuit and signals present internal to the chip. If the value of the monitored signals matches the programmed trigger condition, the trigger register produces a trigger match signal. Each trigger function block receives a combination of the trigger match signals generated by the trigger registers and each computes its programmed boolean minterm function on its inputs. Each trigger function block produces a trigger capture signal which may be true or false according to the computed function of the inputs.