Abstract: In one method according to the present invention, an integrated circuit chip is fabricated by the following steps:1) providing a trial layout in the chip for a victim net and a set of aggressor nets which have segments that lie next to the victim net;2) assigning to the trial layout of the victim net, the parameters of--a line capacitance, a line resistance, and a driver output resistance; and assigning to the trial layout of each aggressor net, the parameters of--a coupling capacitance to the victim net, and a voltage transition;3) estimating, for each aggressor net, a respective peak crosstalk voltage V.sub.p which the aggressor net couples into the victim net as a function V.sub.p =K(e.sup.-X -e.sup.

Abstract: Within an integrated circuit chip, digital logic gates are intercoupled by signal lines called nets. If one net (called the "victim net") has several segments that respectively lie next to several other nets (called "aggressor nets"), then a certain amount of crosstalk voltage will be coupled into the victim net by each of the aggressor nets; and that can cause a malfunction. But with the present invention, a process is provided whereby an integrated circuit chip is physically laid out and built such that the total crosstalk voltage which is coupled into the victim net by all of the aggressor nets is kept within an acceptable level. This process includes a repetitive cycle where during each cycle, a previously tried layout is modified, and the crosstalk which is coupled into the victim net in the modified layout is estimated by means of an equation.

Abstract: Within an integrated circuit chip, digital logic gates are intercoupled by signal lines called nets. If one net (called the "victim net") has several segments that respectively lie next to several other nets (called "aggressor nets"), then a certain amount of crosstalk voltage will be coupled into the victim net by each of the aggressor nets; and that can cause a malfunction. But with the preset invention, a process is provided whereby an integrated circuit chip is physically laid out and built such that the total crosstalk voltage which is coupled into the victim net by all of the aggressor nets is kept within an acceptable level. This process includes a repetitive cycle where during each cycle, a previously tried layout is modified, and the crosstalk which is coupled into the victim net in the modified layout is estimated by means of a table.

Abstract: Transmission line termination circuitry is provided on a driven IC chip utilizing active transistors constructed and arranged so as to steer appropriately directed damping currents into the input bus in a manner which effectively minimizes both overshoot and undershoot without making undue demands on the normally provided chip power supply.