Patents by Inventor Paul G. Villarrubla

Paul G. Villarrubla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Concurrent buffering and layer assignment in integrated circuit layout
    Patent number: 7895557
    Abstract: A method and system for concurrent buffering and layer assignment in integrated current layout. Buffers are inserted and metal interconnects or “wires” are sized for every net, which consists of one driver and one or more receivers, such that timing skew constraints can be met. Long nets are promoted to a higher level if the slew violation can be fixed only by a promotion of the net or if the “slack” gain available by this promotion is equal to or greater than a predesignated layer of promotion threshold. In response to determining these layer assignments, the method and system then systematically demotes nets that are not critical and which do not impact the circuit and electrical constraints in order to minimize the use of high layer wire resources.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Alpert, Zhuo Li, Tuhin Mahmud, Stephen T. Quay, Paul G. Villarrubla
  • Method and System for Concurrent Buffering and Layer Assignment in Integrated Circuit Layout
    Publication number: 20090259980
    Abstract: A method and system for concurrent buffering and layer assignment in integrated current layout. Buffers are inserted and metal interconnects or “wires” are sized for every net, which consists of one driver and one or more receivers, such that timing skew constraints can be met. Long nets are promoted to a higher level if the slew violation can be fixed only by a promotion of the net or if the “slack” gain available by this promotion is equal to or greater than a predesignated layer of promotion threshold. In response to determining these layer assignments, the method and system then systematically demotes nets that are not critical and which do not impact the circuit and electrical constraints in order to minimize the use of high layer wire resources.
    Type: Application
    Filed: April 10, 2008
    Publication date: October 15, 2009
    Inventors: Charles J. ALPERT, Zhuo LI, Tuhin MAHMUD, Stephen T. QUAY, Paul G. VILLARRUBLA