Abstract: A phase-frequency detector (110) is provided. The phase-frequency detector can include a frequency counter delay (147) for counting cycles of an output signal to generate a divided variable frequency delayed signal (FVd 146) having a time shift. A control stage (200) coupled to the output stage generates a pump up control signal (222) and a pump down control signal (234) in response to receiving the FVd signal, a divided variable frequency signal (FV 136), and a reference frequency signal (FR 106). The time shift provides an overlap region that allows both source (350) and sink (360) currents to be provided in phase lock. In phase lock, the duration of the pump up control signal approximates the duration of the pump down control signal within a linear region of operation.

Abstract: In the present technique for managing power of a transmitter on a mobile station, the transmitter power is checked (124) against a training current threshold that can result in the termination of a training ramp during level training mode of the mobile station. Another transmission current threshold is used for comparison (134) with the transmitter current that effectually reduces the power of the transmitter as needed.

Abstract: A DPC (200) that includes: a frequency source (20); a delay-locked loop (220) for receiving a clock signal and generating a plurality of phase-shifted clock signals; a control device (280) having a DPS (282) and a DAC (284) for receiving an input signal identifying a desired frequency for a synthesized signal; a selection circuit (270) for receiving the plurality of phase-shifted clock signals, selecting a sequence of the phase-shifted clock signals and outputting a coarse synthesized signal; a variable delay cell (290) having a first input coupled to the selection circuit to receive the coarse synthesized signal and a second input coupled to the control device for receiving a fine tune adjustment signal to modify the coarse synthesized signal to generate the synthesized signal (292) having substantially the desired frequency. The DPC further includes training apparatus for calibrating the DPC.

Abstract: A power amplifier that includes: an input drive controller (310) for receiving an input signal (312) and for generating from the input signal at least a first drive signal (314), a second drive signal (316), and a third drive signal (318); an outphasing amplifier network (320) coupled to the input drive controller that includes at least a first outphasing amplifier (322) for amplifying the first drive signal and a second outphasing amplifier (326) for amplifying the second drive signal; a peaking amplifier network (330) coupled to the input drive controller that includes at least a first peaking amplifier (332) for amplifying the third drive signal; and a combining network (340) coupled to the outphasing amplifier network and the peaking amplifier network for combining at least the amplified first, second and third drive signals to generate an output signal at a load.

Abstract: A delay-locked loop 300 that includes: an adjustable frequency source (320) for generating a clock signal (322) having an adjustable frequency; an adjustment and tap selection controller (310) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line (330) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit (370) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.