Abstract: A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract: A method, an apparatus, and a computer program are provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.

Abstract: The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.

Abstract: A memory controller capable of handling precharge-to-precharge restrictions is disclosed. Upon commencement of a write operation, the location of the corresponding write precharge command is tracked from a timing standpoint. A determination is then made as to whether or not a subsequent read precharge command will collide with any pending write precharge command. In a determination that a subsequent read precharge command will collide with any pending write precharge command, the issuance of this read precharge command is delayed in order to avoid any collision; also, a specific time interval between this read precharge command and subsequent read precharge commands is maintained.

Abstract: In a first aspect, a first method is provided for adjusting memory system calibration. The first method includes the steps of (1) while in a first operating state, calibrating the memory system using a first amount of calibration data so that functional data may be read from and written to memory of the memory system; and (2) while in a second operating state, calibrating the memory system using a second amount of calibration data so that functional data may be read from and written to the memory, wherein the second amount of calibration data is smaller than the first amount of calibration data. Numerous other aspects are provided.

Abstract: A method, an apparatus, and a computer program product are provided for the handling of write mask operations in an XDR DRAM memory system. This invention eliminates the need for a two-port array because the mask generation is done as the data is received. Less logic is needed for the mask calculation because only 144 of the 256 possible byte values are decoded. The mask value is generated and stored in a mask array. Independently, the write data is stored in a write buffer. The mask value is utilized to generate a write mask command. Once the write mask command is issued, the write data and the mask value are transmitted to a multiplexer. The multiplexer masks the write data using the mask value, so that the masked data can be stored in the XDR DRAMS.

Abstract: A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract: In a first aspect, a first method is provided for storing a command. The first method includes the steps of (1) receiving a new command referencing an address; (2) determining whether the new command is dependent on at least one previously-received command referencing the address stored in a queue of pending commands; (3) identifying the most-recently received command of the at least one previously-received command; and (4) associating the new command with the most-recently received command of the at least one previously-received command. Numerous other aspects are provided.

Abstract: A method, an apparatus, and a computer program are provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.

Abstract: A method, an apparatus, and a computer program are provided to account for data stored in Dynamic Random Access Memory (DRAM) write buffers. There is difficulty in tracking the data stored in DRAM write buffers. To alleviate the difficulty, a cache line list is employed. The cache line list is maintained in a memory controller, which is updated with data movement. This list allows for ease of maintenance of data without loss of consistency.

Abstract: A method, a computer program, and an apparatus are provided for flexible SC to SR mapping to enable sub-page activation in an XDR™ memory system. An XDR™ memory system may allow system page size to reduced by a factor of two (half-page activation) or four (quarter-page activation). In an XDR™ memory system there are five different SCs and two different SRs. This scheme allows any one of the five SCs (or none) to be mapped to any one of the two SRs. Overall, this invention provides a flexible mapping scheme that can be utilized for any possible XDR memory system.

Abstract: A method, apparatus, and computer program product are provided for implementing an enhanced circular queue using loop counts for command processing. A circular queue includes a plurality of entries for storing commands. As command entries are added to the queue at the head of the queue, a head loop count is stored with each command entry. A head pointer is updated to the head of the queue. When the head pointer wraps from a last queue entry to a first queue entry, the head loop count is incremented. A tail pointer points to an oldest command entry, and is updated when the oldest command entry is executed. When the tail pointer advances and wraps from a last queue entry to a first queue entry, the tail pointer loop count is incremented.

Abstract: A method, an apparatus, and a computer program are provided for the separate handling of read and write operations of Read-Modify-Write Commands in an XDR™ memory system. This invention allows the system to issue other commands between the reads and writes of a RMW. This insures that the dataflow time from read to write is not a penalty. A RMW buffer is used to store the read data and a write buffer is used to store the write data. A MUX is used to merge the read data and the write data, and transmit the merged data to the target DRAM via the XIO. The RMW buffer can also be used for scrubbing commands.

Abstract: In a first aspect, a method for maintaining control structure coherency is provided. The method includes the steps of (1) writing a pointer to a control structure in a hardware update list while one or more portions of the control structure are accessed by hardware during a hardware update operation; and (2) delaying a software access to one or more portions of the control structure during a software update operation while the pointer to the control structure is on the hardware update list. Numerous other aspects are provided.

Abstract: A method, apparatus, and computer program product are provided for implementing packet ordering in a network processor. Packets are received and placed on a receive queue and a queue entry is provided for each received packet. The queue entry includes for each autoroute packet, an autoroute indication and a selected transmit queue. An associated ordering queue is provided with the receive queue. A software-handled packet is dequeued from the receive queue and the dequeued software-handled packet is placed on the ordering queue. Each autoroute packet reaching a head of the receive queue is automatically moved to the selected ordering queue.