Abstract: A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage and temperature, and a design structure on which the subject circuit resides is provided. A clock source is coupled to an N-level balanced clock tree providing a clock signal. Each of a plurality of voltage islands includes a respective voltage shifter and programmable delay function receiving the clock signal. Each respective voltage shifter and programmable delay function provides a second clock signal to a respective balanced clock tree for the associated voltage island. A system controller provides a respective control input to each respective voltage shifter and programmable delay function. The respective control input is varied dynamically corresponding to an operational mode of the respective voltage island.

Abstract: A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage and temperature, and a design structure on which the subject circuit resides is provided. A clock source is coupled to an N-level balanced clock tree providing a clock signal. Each of a plurality of voltage islands includes a respective voltage shifter and programmable delay function receiving the clock signal. Each respective voltage shifter and programmable delay function provides a second clock signal to a respective balanced clock tree for the associated voltage island. A system controller provides a respective control input to each respective voltage shifter and programmable delay function. The respective control input is varied dynamically corresponding to an operational mode of the respective voltage island.

Abstract: A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.

Abstract: A tool for designing integrated circuits that optimizes the placement and timing of memory blocks within the circuit. Given a manufactured slice that has a number of blocks already diffused and logically integrated, the memory generation tool herein automatically considers the available diffused memory and the gate array of the slices to configure and optimize them into a customer's requirements for memory. The memory generation tool has a memory manager, a memory resource database, a memory resource selector, and a memory composer. Together these all interact to generate memories from the available memories within the memory resource database. The memory composer actually generates the RTL logic shells for the memories, and outputs the memory designs in Verilog, VHDL, or other tool synthesis language. Once a memory is created, it is tested.

Abstract: A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.

Abstract: A register address generation tool is used during the design of semiconductor products. For those registers and/or memories that are addressable on a bus, the register address generation tool creates the interconnect RTL, header files, static timing analysis constraint files, and verification testcases. The tool also maintains coherence between what has been generated and the available resources for the design of the semiconductor product in a design. If there are any registers and/or memories that are not being used, the register address generation tool may further generate the RTL that will convert these unused resources to performance-enhancing features such as control registers, status registers, etc. The register address generation tool read a design database having an application set to determine what hardmacs and what transistor fabric is available. It also receives as input a bus specification and address parameters.

Abstract: A register address generation tool is used during the design of semiconductor products. For those registers and/or memories that are addressable on a bus, the register address generation tool creates the interconnect RTL, header files, static timing analysis constraint files, and verification testcases. The tool also maintains coherence between what has been generated and the available resources for the design of the semiconductor product in a design. If there are any registers and/or memories that are not being used, the register address generation tool may further generate the RTL that will convert these unused resources to performance-enhancing features such as control registers, status registers, etc. The register address generation tool read a design database having an application set to determine what hardmacs and what transistor fabric is available. It also receives as input a bus specification and address parameters.

Abstract: A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.

Abstract: A tool for designing integrated circuits that optimizes the placement and timing of memory blocks within the circuit. Given a manufactured slice that has a number of blocks already diffused and logically integrated, the memory generation tool herein automatically considers the available diffused memory and the gate array of the slices to configure and optimize them into a customer's requirements for memory. The memory generation tool has a memory manager, a memory resource database, a memory resource selector, and a memory composer. Together these all interact to generate memories from the available memories within the memory resource database. The memory composer actually generates the RTL logic shells for the memories, and outputs the memory designs in Verilog, VHDL, or other tool synthesis language. Once a memory is created, it is tested.

Abstract: An Input/Output (I/O) adapter for use with a second I/O adapter in a clustered configuration. The I/O adapter includes a dedicated communication link, such as a high-speed serial bus, that provides for communication between the I/O adapter and the second I/O adapter. The I/O adapter also includes a message passing circuit, coupled to the dedicated communication link, that allows for transferring of data between the I/O adapter and the second I/O adapter. The I/O adapter further includes a doorbell circuit, coupled to the message passing circuit, that generates interrupts to provide a low level communication between the I/O adapter and the second I/O adapter. A mirroring directory, coupled to the message passing circuit, is also included in the I/O adapter to provide for the mirroring of cache directory writes.

Abstract: A storage area network (SAN) fibre channel arbitrated loop (FCAL) multiple system, multiple resource, storage enclosure and a method are provided for performing enclosure maintenance concurrent with device operations. The storage enclosure includes a plurality of storage resources or storage devices, a plurality of IO adapters (IOAs) coupled to the storage area network and a pair of enclosure services node cards. Each enclosure services node card includes loop connections for the plurality of storage resources. Each enclosure services node card includes a respective global bus connection and a loop connection to each of the plurality of IOAs. Each enclosure services node card is used concurrently by the multiple systems to manage the plurality of storage resources. In the method for performing enclosure maintenance concurrent with device operations, identical maintenance procedures are implemented for the enclosure services node cards and the storage devices.

Abstract: A method for maintaining data coherency in a dual Input/Output(I/O) adapter having primary and secondary adapters, wherein each of the primary and secondary adapters includes resident write cache data and directory storage devices. The method includes utilizing a split point to separate each of the cache data and directory storage devices into first and second regions, wherein the first regions contain the primary adapter cache data and directory information and the second regions contain the secondary adapter cache data and directory information. Information stored in the primary adapter cache data and directory storage devices is mirrored into the secondary adapter cache data and directory storage devices or, alternatively, information stored in the secondary adapter cache data and directory storage devices is mirrored into the primary adapter cache data and directory storage devices utilizing a dedicated communication link, such as a high-speed serial bus, between the primary and secondary adapters.

Abstract: A method for maintaining data coherency in a dual Input/Output(I/O) adapter having primary and secondary adapters, wherein each of the primary and secondary adapters includes resident write cache data and directory storage devices. The method includes utilizing a split point to separate each of the cache data and directory storage devices into first and second regions, wherein the first regions contain the primary adapter cache data and directory information and the second regions contain the secondary adapter cache data and directory information. Information stored in the primary adapter cache data and directory storage devices is mirrored into the secondary adapter cache data and directory storage devices or, alternatively, information stored in the secondary adapter cache data and directory storage devices is mirrored into the primary adapter cache data and directory storage devices utilizing a dedicated communication link, such as a high-speed serial bus, between the primary and secondary adapters.

Abstract: An Input/Output (I/O) adapter for use with a second I/O adapter in a clustered configuration. The I/O adapter includes a dedicated communication link, such as a high-speed serial bus, that provides for communication between the I/O adapter and the second I/O adapter. The I/O adapter also includes a message passing circuit, coupled to the dedicated communication link, that allows for transferring of data between the I/O adapter and the second I/O adapter. The I/O adapter further includes a doorbell circuit, coupled to the message passing circuit, that generates interrupts to provide a low level communication between the I/O adapter and the second I/O adapter. A mirroring directory, coupled to the message passing circuit, is also included in the I/O adapter to provide for the mirroring of cache directory writes.

Abstract: A storage area network (SAN) fibre channel arbitrated loop (FCAL) multiple system, multiple resource, storage enclosure and a method are provided for performing enclosure maintenance concurrent with device operations. The storage enclosure includes a plurality of storage resources or storage devices, a plurality of IO adapters (IOAs) coupled to the storage area network and a pair of enclosure services node cards. Each enclosure services node card includes loop connections for the plurality of storage resources. Each enclosure services node card includes a respective global bus connection and a loop connection to each of the plurality of IOAs. Each enclosure services node card is used concurrently by the multiple systems to manage the plurality of storage resources. In the method for performing enclosure maintenance concurrent with device operations, identical maintenance procedures are implemented for the enclosure services node cards and the storage devices.

Abstract: A communication system for an array of DASD includes a plurality of loop resiliency circuits and a plurality of selection circuits. The DASD array includes a plurality of DASD slots. Each DASD slot may receive a DASD, and each DASD receives power from a regulator. The loop resiliency circuits form at least a first communication path. Each loop resiliency circuit is associated with one of the DASD slots and selectively includes the associated DASD slot in the first communication path based on a selection signal. The plurality of selection circuits are also associated with one of the DASD slots; and therefore, are also associated with one of the plurality of loop resiliency circuits. Each selection circuit is connected to the associated DASD slot and receives output from the regulator in the associated DASD slot. Based on the regulator output, or a lack thereof, the selection circuit generates a selection signal for the associated loop resiliency circuit.