Abstract: A serial communications device comprises a controller to obtain digital diagnostic data representative of operational characteristics of the serial communications device, memory to store the digital diagnostic data and at least one interface, including an interface to serially communicate data via a serial cable. The serial communications device also comprises a signal controller configured to encode the digital diagnostic data onto a serial data signal for transmission via the serial cable by adjusting signal levels of the serial data signal while preserving original data in the serial data signal. Encoding the digital diagnostic data includes serializing the digital diagnostic data, determining a series of signal levels for the serialized digital diagnostic data based on a signal encoding map, and adjusting signal levels for the serial data signal based on the determined series of signal levels.

Abstract: A serial communications device comprises a controller to obtain digital diagnostic data representative of operational characteristics of the serial communications device, memory to store the digital diagnostic data and at least one interface, including an interface to serially communicate data via a serial cable. The serial communications device also comprises a signal controller configured to encode the digital diagnostic data onto a serial data signal for transmission via the serial cable by adjusting signal levels of the serial data signal while preserving original data in the serial data signal. Encoding the digital diagnostic data includes serializing the digital diagnostic data, determining a series of signal levels for the serialized digital diagnostic data based on a signal encoding map, and adjusting signal levels for the serial data signal based on the determined series of signal levels.

Abstract: The serial communication device includes a first module coupled to a second module via a serial cable. Each of the first and second modules comprise one or more of: a power interface, a controller, memory, a first interface, and a second interface. The power interface is configured to receive operating power for the respective module from an external power source. The controller is configured to obtain digital diagnostic data representative of operational characteristics of at least the respective module. The memory is configured to store the digital diagnostic data. The first interface is configured to allow an external host to read the digital diagnostic data from the memory. The second interface, which is distinct and separate from the first interface, is configured to serially communicate data to the second module via the serial cable.

Abstract: A network tap device that is configured for operation in a copper Gigabit Ethernet communications network using a power-over-Ethernet (“POE”) electrical supply is disclosed. In one embodiment, a network tap device powered by a POE supply is disclosed, comprising first and second network ports that are configured with receptacles for receiving communication cables. The communication cables are configured to carry both data signals and the POE supply to and from the network tap device. The network tap device further includes first and second tap ports that connect with additional communication cables to a monitoring device. The network tap device also includes control and regulation circuitry that is configured to receive the POE supply from the communication cables via the network ports and to enable components of the network tap device to be operated by the POE supply.

Abstract: A network tap device array capable of being powered by a power-over Ethernet (“POE”) supply is disclosed. The array enables data from multiple nodes in a communications network to be tapped and forwarded to a plurality of monitoring devices. In one embodiment the network tap device array includes a chassis that is configured to receive a plurality of network tap devices that are each powered by a POE supply. Each network tap device includes network ports for receiving and transmitting network data via communication cables and tap ports for forwarding the tapped network data to the monitoring device. In another embodiment, a sub-chassis includes a plurality of network tap devices and an aggregator that aggregates tapped data from each of the tap devices. The aggregator then forwards the aggregated data to the monitoring device. The sub-chassis can be included in a chassis that is configured to receive multiple populated chassis.

Abstract: Methods and apparatuses for using interpolation to associate timestamp values to data received in a data capture and analysis system. An analysis processor receives data representing data transferred in a communications link. The analysis processor also receives timestamp signals. The analysis processor performs an interpolation between at least two timestamp values received and associates results of the interpolation with the data. The analysis processor analyzes the data. A logic device can be coupled to the analysis processor to interleave timestamp signal values with the data and transmit the interleaved data and timestamp signals to the analysis processor.

Abstract: The serial communication bus includes a first module coupled to a second module via a serial cable. Each of the first and second modules comprise one or more of: a power interface, a controller, memory, a first interface, and a second interface. The power interface is configured to receive operating power for the respective module from an external power source. The controller is configured to obtain digital diagnostic data representative of operational characteristics of at least the respective module. The memory is configured to store the digital diagnostic data. The first interface is configured to allow an external host to read the digital diagnostic data from the memory. The second interface, which is distinct and separate from the first interface, is configured to serially communicate data to the second module via the serial cable.

Abstract: Interposers for tapping a signal. An interposer can include an interposer printed circuit board, an output connector that couples the interposer circuit board with a backplane connector of a chassis, an input connector for coupling the interposer circuit board with a disk drive, tapping circuitry for tapping a high-speed differential signal, and connectors coupled to the tapping circuitry for transmitting the tapped signal to an analyzer or an oscilloscope.

Abstract: A passive full-duplex bidirectional ZPL tap includes first and second network ports and tap ports. A signal separator is configured to receive a data stream from at least one of the first or second network ports and pass through the data stream and configured to obtain a first signal portion comprising at least the first signal component and obtain a second signal portion comprising at least the second signal component. A DSP stage is configured to substantially remove any second data component from the first signal portion and to substantially remove any first data component from the second signal portion. A first receive only Phy is configured to receive the first signal portion and provide the first signal portion to the first tap port and a second receive only Phy is configured to receive the second signal portion and provide the second signal portion to the second tap port.

Abstract: A receive or listen only Physical Interface Device (Phy). The receive or listen only Phy is configured to have a front end configured to only receive data from a communications network. The receive only Phy may be implemented a part of a tap device including a first network port for receiving a first network signal having a first format; a receive only Phy for converting the first network signal into a second signal format; and a transmit and receive Phy for receiving the first network signal in the second signal format and converting it into the first signal format.

Abstract: The principles of the present invention relate to passive full-duplex bidirectional Zero Packet Loss (ZPL) network taps that include single, dual, or dual differential couplers that are placed in the communication path between two network devices that communicate using a full-duplex bidirectional data stream that include a first and a second data component. The bidirectional couplers are configured to at least partially obtain a second data stream that includes at least the first data component and to obtain a third data stream that includes at least the second data component. In some embodiments, the bidirectional couplers may include a signal separation module or stage that is configured to further separate the first and second data components.

Abstract: A network tap device array including one or more passive full-duplex bidirectional ZPL network tap devices is disclosed. The array enables data from multiple nodes in a communications network to be tapped and forwarded to a plurality of monitoring devices. In one embodiment the network tap device array includes a chassis that is configured to receive a plurality of passive full-duplex bidirectional ZPL network tap devices. Each passive full-duplex bidirectional ZPL network tap device includes network ports for passing network data via communication cables and tap ports for forwarding the tapped network data to the monitoring device. In another embodiment, a sub-chassis includes a plurality of passive full-duplex bidirectional ZPL network tap devices and an aggregator that aggregates tapped data from each of the tap devices. The aggregator then forwards the aggregated data to the monitoring device. The sub-chassis can be included in a chassis that is configured to receive multiple populated chassis.

Abstract: An bit error rate tester for use in connection with a high speed networks. The bit error rate tester includes transmit and receive ports, as well as a sequence generator, memory, synchronizer, sequence start detect module, and comparator. The sequence generator generates a bit sequence for transmission through a network path. The bit sequence returns to the bit error rate tester by way of the receive port. The synchronizer then bit-aligns the received bit sequence to compensate for idles/fill words added/dropped as the bit sequence transited the network. The synchronized bit sequence is passed to the start word detector which detects start and end words in the bit sequence and instructs the comparator to compare only data between the start and end words. The comparator compares the received bit sequence with a copy of the transmitted bit sequence regenerated from the memory, and calculates a bit error rate.

Abstract: A network tap device array capable of being powered by a power-over Ethernet (“POE”) supply is disclosed. The array enables data from multiple nodes in a communications network to be tapped and forwarded to a plurality of monitoring devices. In one embodiment the network tap device array includes a chassis that is configured to receive a plurality of network tap devices that are each powered by a POE supply. Each network tap device includes network ports for receiving and transmitting network data via communication cables and tap ports for forwarding the tapped network data to the monitoring device. In another embodiment, a sub-chassis includes a plurality of network tap devices and an aggregator that aggregates tapped data from each of the tap devices. The aggregator then forwards the aggregated data to the monitoring device. The sub-chassis can be included in a chassis that is configured to receive multiple populated chassis.

Abstract: A network tap device that is configured for operation in a copper Gigabit Ethernet communications network using a power-over-Ethernet (“POE”) electrical supply is disclosed. In one embodiment, a network tap device powered by a POE supply is disclosed, comprising first and second network ports that are configured with receptacles for receiving communication cables. The communication cables are configured to carry both data signals and the POE supply to and from the network tap device. The network tap device further includes first and second tap ports that connect with additional communication cables to a monitoring device. The network tap device also includes control and regulation circuitry that is configured to receive the POE supply from the communication cables via the network ports and to enable components of the network tap device to be operated by the POE supply.

Abstract: A networking system is provided. The networking system may include a diagnostic module. The diagnostic module may perform any of a variety of network diagnostic functions. A diagnostic module may include an oscillator module. The oscillator module may be configured to provide a variety of clock signals to support a variety of network protocols and/or data rates.

Abstract: Methods and apparatuses for using interpolation to associate timestamp values to data received in a data capture and analysis system. An analysis processor receives data representing data transferred in a communications link. The analysis processor also receives timestamp signals. The analysis processor performs an interpolation between at least two timestamp values received and associates results of the interpolation with the data. The analysis processor analyzes the data. A logic device can be coupled to the analysis processor to interleave timestamp signal values with the data and transmit the interleaved data and timestamp signals to the analysis processor.

Abstract: An bit error rate tester for use in connection with a high speed networks. The bit error rate tester includes transmit and receive ports, as well as a sequence generator, memory, synchronizer, sequence start detect module, and comparator. The sequence generator generates a bit sequence for transmission through a network path. The bit sequence returns to the bit error rate tester by way of the receive port. The synchronizer then bit-aligns the received bit sequence to compensate for idles/fill words added/dropped as the bit sequence transited the network. The synchronized bit sequence is passed to the start word detector which detects start and end words in the bit sequence and instructs the comparator to compare only data between the start and end words. The comparator compares the received bit sequence with a copy of the transmitted bit sequence regenerated from the memory, and calculates a bit error rate.

Abstract: Interposers for tapping a signal. An interposer can include an interposer printed circuit board, an output connector that couples the interposer circuit board with a backplane connector of a chassis, an input connector for coupling the interposer circuit board with a disk drive, tapping circuitry for tapping a high-speed differential signal, and connectors coupled to the tapping circuitry for transmitting the tapped signal to an analyzer or an oscilloscope.

Abstract: The present invention is a bit error rate tester that may operate on network paths having devices that add or drop idles within a transmitted bit sequence. In particular, the bit sequence determines whether a received bit sequence is synchronized. If the received sequence is not synchronized or if a certain event/threshold is reached, then the bit error rate tester re-synchronizes the sequence prior to analysis. Also, the bit error rate detector is able to operate on high-speed networks and provide bit granularity measurements.