Abstract: A system and computer program product for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces the density below a predetermined threshold. The method acts to control the movement of different cells to reduce the density of the cells prior to legalization of the cell placement.

Abstract: A method for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces the density below a predetermined threshold. The method acts to control the movement of different cells to reduce the density of the cells prior to legalization of the cell placement.

Abstract: A placement technique for designing a layout of an integrated circuit by calculating clustering scores for different pairs of objects in the layout based on connections of two objects in a given pair and the sizes of the two objects, then grouping at least one of the pairs of objects into a cluster based on the clustering scores, partitioning the objects as clustered and ungrouping the cluster after partitioning. The pair of objects having the highest clustering score are grouped into the cluster, and the clustering score is directly proportional to the total weight of connections between the two objects in the respective pair. The clustering scores are preferably inserted in a binary heap to identify the highest clustering score. After grouping, the clustering score for any neighboring object of a clustered object is marked to indicate that the clustering score is invalid and must be recalculated. The calculating and grouping are then repeated iteratively based on the previous clustered layout.

Abstract: A method of assessing the stability of a placement tool used in designing the physical layout of an integrated circuit chip, by constructing different layouts of cells using the placement tool with different sets of input parameters, and calculating a stability value based on the movement of respective cell locations between the layouts. The stability value can be normalized based on cell locations in a random placement. One stability metric measures absolute movement of individual cells in the layouts, weighted by cell area. The cell movements can be squared in calculating the stability value. Another stability metric measures the relative movement of cells with respect to their nets. Shifting of cells and symmetric reversal of cells about a net center does not contribute to this relative movement, but spreading of cells and rotation of cells with respect to the net center does contribute to the relative movement. Relative cell movements can again be squared in calculating the stability value.

Abstract: A method (and system) of applying transforms for modifying a plurality of domains concurrently in a design space, includes creating a sequence of more and less granular placement and netlist modification transforms. A converging design process flow is created by a flexible mechanism in which a select combination of fine-grained transforms are applied to optimize the netlist and placement of a design.

Abstract: A method of designing an integrated circuit including executing a placement algorithm to place a set of objects within the integrated circuit. The set of objects includes latched objects and non-latched objects. The algorithm places objects to minimize clock signal delay subject to a constraint on the placement distribution of the latched objects relative to the placement distribution of the non-latched objects. The latched object and non-latched object placement constraints may limit the difference between the latched object center of mass and a non-latched object center of mass. The latched object center of mass equals a sum of size-location products for each latched object divided by the sum of sizes for each latched object. The constraints may require that the latched object center of mass and the non-latched center of mass both equal the center of mass for all objects.

Abstract: A method, system, and computer program product for allocating buffer and wire placement in an integrated circuit design is provided. In one embodiment, the surface of a integrated circuit design is represented as a tile graph. Allocation of buffer locations for selected tiles in the tile graph is then received and nets are routed between associated sources and sinks. Buffer locations within selected tiles are then selectively assigned based upon buffer needs of the nets, wherein the nets are routed through selected tiles and assigned buffer locations using a cost minimization algorithm.

Abstract: This invention reduces pessimism in cross talk analysis of digital circuits by combining only the peak noises from aggressor nets that can switch simultaneously during the time interval when the downstream receiving latch can sample the errant data. This is done by, first, determining aggressor switching windows and victim sensitivity windows. These windows are then used to determine which combination of noise sources can temporally align so as to cause the greatest noise within the victim sensitivity window.

Abstract: A method, system, and computer program product for allocating buffer and wire placement in an integrated circuit design is provided. In one embodiment, the surface of a integrated circuit design is represented as a tile graph. Allocation of buffer locations for selected tiles in the tile graph is then received and nets are routed between associated sources and sinks. Buffer locations within selected tiles are then selectively assigned based upon buffer needs of the nets, wherein the nets are routed through selected tiles and assigned buffer locations using a cost minimization algorithm.

Abstract: A method for performing circuit analysis on an integrated-circuit design having design data available in different forms is disclosed. In accordance with the method and system of the present invention, the integrated-circuit design includes multiple networks, and the different forms of design data may appear within one of the networks. For all of the networks within the integrated-circuit design, different forms of design data are categorized into at least three databases. The first of the at least three databases may contain three-dimensional extraction information, the second of the databases may contain wiring information, and the third of the databases may contain pre-wiring information. For each of the networks, a determination is made as to whether or not three-dimensional extraction information is available. In response to a determination that three-dimensional extraction information is available, performing circuit analysis by utilizing the three-dimensional extraction information.

Abstract: A method and system are disclosed for efficiently storing and viewing data in a database. Data is stored in a nested data model which includes a plurality of nodes. A plurality of edges connect the plurality of nodes. Each edge has a unique edge name. A plurality of instances of data objects are associated with the nested data model. Each instance is associated with one of the edges such that the instance is also associated with that edge's name. An instance ordinal is associated with each instance which represents the number of times the edge associated with each instance is encountered during a traversal of the nested data model. The data stored utilizing the nested data model is accessed utilizing the instance ordinal and edge name associated with each of the plurality of instances, such that the data is accessed as being flat without flattening the nested data model.

Abstract: A method and system for performing timing analysis on an integrated circuit design are disclosed. It is always advantageous to be able to conveniently perform a timing analysis on the entire IC design at any stage of the design process in order to gain more accurate timing information about the design. However, at an early stage of the design process, the available physical circuit data are often incomplete, not to mention these preliminary data are usually of a lower quality as far as capability of providing an accurate RC delay and capacitance estimation is concerned. To make the best usage of the preliminary data, the present disclosure describes a method of performing a fleeting timing analysis that can be very useful during an early floor planning stage of the design process when there is no opportunity to buffer or widen any exceptionally long interconnect wires within the IC circuit design.

Abstract: A method and system for shape processing within an integrated circuit layout for parasitic capacitance estimation is disclosed. In accordance with the method and system of the present invention, a set of coordinates of an overlapping region formed by at least one interconnect is first identified. Subsequently, each metal layer present within the overlapping region is classified. Each interconnect edge present on each side of the overlapping region is then determined. Finally, a neighbor in a direction perpendicular to each side of the overlapping region is determined. By so doing, the parasitic capacitance between the overlapping region and its determined neighbors can be evaluated.

Abstract: One aspect of the invention relates to a method for improving timing convergence in computer aided semiconductor circuit design. In one particular version of the invention, the method includes the steps of generating a behavioral model of a desired semiconductor circuit, which includes timing constraints for individual paths in the circuit, synthesizing the behavioral model to produce a netlist which represents an implementation of the desired semiconductor circuit mapped to a specific semiconductor technology, the netlist including a list of components in the circuit and a list of nets which connect the components in the circuit, and the step of synthesizing includes performing a timing analysis on the implementation so that the paths in the circuit represented by the netlist meet the timing constraints, the timing analysis being performed using estimated wire lengths for the nets. Next, the components in the netlist are placed into an image representing a predefined area of the semiconductor chip.

Abstract: A system and method are provided for distributing clock signals within integrated circuitry. The system includes a number of cells for the integrated circuitry such that the cells include substantially horizontal regions within which are disposed substantially horizontal lines representative of a first clock. The cells also include substantially vertical regions within which are disposed vertical lines representative of a second clock. The cells are disposed in substantially horizontal layers. The vertical regions, including the vertical lines representative of a second clock are substantially vertically aligned. The cells include circuitry disposed within each cell such that a first portion of such circuitry includes signal wiring, and a second portion of such circuitry includes clock wiring, and such that the disposition of said circuitry minimizes a cumulative length of signal wiring and clock wiring.

Abstract: A method and system for providing parasitic capacitance estimation on interconnect data for an integrated circuit is disclosed. An integrated circuit typically includes a substrate layer and several metal layers. In accordance with the method and system of the present invention, a center wire within one of the several metal layers is first identified. Then, a first capacitance value between a first wire and the center wire as well as a second capacitance value between a second wire and the center wire are determined. The first wire, the second wire, and the center wire are in the same metal layer. Next, a third capacitance value between a third wire and the center wire is determined. This third wire is in a metal layer located directly beneath the center wire. Finally, a fourth capacitance value between a fourth wire and the center wire is determined. The fourth wire is in a metal layer located directly above the center wire.

Abstract: A method and system for characterizing interconnect data within an integrated circuit in order to facilitate parasitic capacitance estimation is disclosed. An integrated circuit typically includes a substrate layer and several metal layers. In accordance with the method and system of the present invention, an overlapping area of interconnect wires is first identified within the integrated circuit. This overlapping area, which is a polygon, may be formed between the substrate layer and at least one interconnect wire in one of the several metal layers. The overlapping area may also be formed between two interconnect wires, each in a different one of the several metal layers. A netname for the overlapping area is then recorded. Finally, a netname of an interconnect wire in a metal layer that is at the same level of an interconnect wire within the overlapping area and an associated distance from each side of the overlapping area is recorded, for every interconnect wire within the overlapping area.