Patents by Inventor Paul Godtland

Paul Godtland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070208882
    Abstract: An operating system kernel includes an attach mechanism and a detach mechanism. In addition, processes are tagged with an access attribute identifying the process as either a client process or a server process. Based on the access attribute, the operating system kernel lays out the process local address space differently depending on whether the process is a client process or a server process. A server process can “attach” to a client process and reference all of the client process' local storage as though it were its own. The server process continues to reference its own process local storage, but in addition, it can reference the other storage, using the client process' local addresses. When access to the other storage is no longer needed, the server process can “detach” from the client process. Once detached, the other storage can no longer be referenced.
    Type: Application
    Filed: February 23, 2006
    Publication date: September 6, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Corrigan, Paul Godtland, Richard Kirkman, Wade Ouren, George Timms
  • Publication number: 20070143565
    Abstract: An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.
    Type: Application
    Filed: December 15, 2005
    Publication date: June 21, 2007
    Applicant: International Business Machines Corporation
    Inventors: Michael Corrigan, Paul Godtland, Joaquin Hinojosa, Cathy May, Naresh Nayar, Edward Silha
  • Publication number: 20070033572
    Abstract: A program feature set is compared to a processor feature set. The comparison may be performed in response to restoring the program onto a system or requesting its execution. The processor feature set represents zero, one or more optional hardware features supported by the processor, whereas the program feature set represents zero, one or more optional hardware features the program relies upon in its generated code. Comparison of the feature sets determines whether a particular program may run on a particular processor. Programs may be automatically or manually rebuilt to achieve full compatibility. If the comparison indicates that the program requires a feature not supported by the processor, the program is rebuilt based on the processor feature set. Alternatively, the program may be rebuilt in response to a rebuild request, rather than the comparison. The program is preferably rebuilt from an intermediate representation (IR) stored with or locatable from the program.
    Type: Application
    Filed: August 4, 2005
    Publication date: February 8, 2007
    Applicant: International Business Machines Corporation
    Inventors: Robert Donovan, Paul Godtland, Sherri McMeeking, Joseph Reynolds, Scott Robinson, Robert Roediger, William Schmidt, Roger Southwick