Abstract: An apparatus and method for providing a transient connection port are provided. Further, an apparatus and method for switching between a permanent connection port and a transient connection port are provided. The apparatus and method include a permanent connection port and a transient connection port located at the rear of a rack mounted server system and the front of the rack mounted server system, respectively. The permanent connection port operates when there is an absence of a connected device at the transient connection port. When a device is connected to the transient connection port, a signal is sent to a logic switch which causes the active input to be switched from the permanent connection port to the transient connection port. When the device is no longer connected to the transient connection port, the absence of the signal from the transient connection port causes the logic switch to switch the active input back to the permanent connection port.

Abstract: A system and method are provided for detecting when a valid configuration of I/O adapters is present in the system board of a computer. The present invention is a mechanism that allows the system user to determine the configuration of the I/O adapter cards to be used, independent of their voltage levels. More particularly, if the programmed voltage of the computer system power supply is compatible with the desired adapter card, the present invention will allow the card to be inserted and used. The present invention includes a connector that is physically capable of receiving any one of a variety of adapter cards, independent of the operating voltage level of the adapter cards. The present invention is a mechanism for detecting a valid mix of adapter cards inserted into connectors on the system board of a computer. When adapter cards having different voltage ratings are inserted into the slots, power on operations are not allowed preventing possible damage to the computer.

Abstract: The invention provides an apparatus and method of allowing a device to respond to a configuration query only if it is the true target of the query. In one embodiment of the invention, logic gates having two inputs are provided. The first input of the logic gates is connected to the signal of a bridge that selects a device when the address of the signal is referenced in the configuration query. The second input of the logic gate receives a signal indicating whether the local bus or the subordinate bus is being configured and the output of the logic gate is used to enable the device. In a second embodiment, certain signals designated to indicate the selection of a bus are used to enable devices to respond to configuration queries.

Abstract: A process and implementing computer system in which an arbitration circuit is comprised of a plurality of state machines 301, 303 and 305 which combine to receive various system timing signals and provide a data bus grant signal effective to enable data streaming of sequential data blocks of information from an L2 cache memory 109 without intervening wait states between the data blocks.

Abstract: A process and implementing system is provided for conducting a memory test for isolating and identifying failed cache memory modules in a memory subsystem of a computer system. The methodology initially selects 303 a block of memory which is twice the size of the cache 105 being tested. The cache 105 is then disabled 305 and a first test is performed 307 on the selected block of to isolate byte addresses of individual bit failures. If bit failures are detected 308, the appropriate byte address is mapped 310 and the test is ended 321. If no bit errors are detected in the first test, the cache is enabled 309 and a second test is performed and the block is tested 311 for failures. Any detected failures are assumed to be cache failures and the appropriate byte address is mapped 315. The cache is again disabled 317. An appropriate message is then displayed 319 to indicate the results of the testing.

Abstract: A computer system and arbitrator prevent a livelock condition from occurring between a host bus bridge and a PCI bridge, where the host bus bridge and PCI bridge conform to the specification delineated in the PCI-to-PCI Bridge Architecture Specification 1.0 and PCI Local Bus Specification 2.0. The system includes an arbitrator for masking from the PCI bridge a request (REQ.sub.--) generated by a device on a second bus. The arbitrator requests that the host bus bridge flush all existing I/O requests (FLUSHREQ.sub.--) and postpone any future I/O requests from a central processing unit. The third step includes, in response to a notification from the host bus bridge that all I/O requests have been flushed and that any future I/O requests from the central processing unit will be postponed (MEMACK.sub.--), the arbitrator unmasks the request to the PCI bridge (GREQ.sub.--). In response to unmasking the request to the PCI bridge, the PCI bridge grants control of the second bus to the device (GNT.sub.--).

Abstract: A method prevents a livelock condition from occurring between a host bus bridge (e.g., memory controller) and a PCI bus bridge, where the host bus bridge and PCI bus bridge conform to the specification delineated in the PCI-to-PCI Bridge Architecture Specification 1.0 and PCI Local Bus Specification 2.0. The method includes the first step of masking from the PCI bridge a request generated by a device on a second bus. The second step includes requesting that the host bus bridge flush all existing I/O requests and postpone any future I/O requests from a central processing unit. The third step includes, in response to a notification from the host bus bridge that all I/O requests have been flushed and that any future I/O requests from the central processing unit will be postponed, unmasking the request to the PCI bridge. The fourth step includes, in response to unmasking the request to the PCI bus bridge, granting access of the second bus from the PCI bus bridge to the device.

Abstract: A method prevents a livelock condition from occurring between a host bus bridge and a PCI bridge, where the host bus bridge and PCI bridge conform to the specification delineated in the PCI-to-PCI Bridge Architecture Specification 1.0 and PCI Local Bus Specification 2.0. The method includes the first step of in response to at least first and second requests being substantially simultaneously received from at least first and second peripherals, determining if a state of a state machine corresponds to an assigned order of either the first peripheral or the second peripheral. The second step includes if the state does not correspond to the assigned order of the first peripheral or the second peripheral, advancing the state and repeating the first step until the state corresponds to one of the first or second peripherals. The third step includes if the state corresponds to the assigned order of either the first or second peripheral, determining if the selected request targets system memory.