Abstract: The invention relates to a data switch, comprising: plural input ports each for receiving data cells from a respective link; plural output ports each for providing data cells to a respective link; a switch fabric for selectively enabling a data cell received at one of the plural input ports to be switched to one or more of the plural output ports; and a switch scheduler comprising a cut-through arbiter arranged to schedule the switching of a received data cell before the entirety of the data cell is received.

Abstract: A data switch is proposed of the type having virtual queue ingress routers interconnected with egress routers by way of a memoryless switching matrix controlled by a control unit which performs an arbitration process to schedule connections across the switch. This scheduling is performed to ensure that data cells which arrive at the ingress routers at unpredictable times are transmitted to the correct egress routers. Each ingress router further includes a queue for time division multiplex traffic, and at times when such traffic exists, the control unit overrides the arbitration process to allow the time division multiplex traffic to be transmitted through the switch.

Abstract: In a data switching system, the ingress and egress ports of a memoryless cross-bar switch are controlled by an arbitration method. The arbitration method uses a three phase process involving (i) a request phase in which each ingress port sends its connection requests to egress ports to which a connection is required, (ii) a grant phase in which each egress port uses a grant pointer to select one of the requests directed to it using a grant pointer, and generates a grant signal, and (iii) an accept phase in which each ingress port selects one of the received grant signals to accept, so defining an ingress to egress port connection across the cross-bar switch. The transition sequences for each of the grant pointers are mutually exclusive, so that any synchronisation of the grant pointers is eliminated on the next arbitration cycle. This is arranged by a setting of the paths taken by request and grant signals.

Abstract: A scheduling means for data switching apparatus includes a plurality of input ports and a plurality of output ports, the scheduling means capable of processing a plurality of interconnection requests, each requesting interconnection between a sub-set of the input ports and a sub-set of respective the output ports, and each request having a respective priority level which is one of a predetermined number of priority levels.

Abstract: A data switch is proposed of the type having virtual queue ingress routers interconnected with egress routers by way of a memoryless switching matrix controlled by a control unit which performs an arbitration process to schedule connections across the switch. This scheduling is performed to ensure that data cells which arrive at the ingress routers at unpredictable times are transmitted to the correct egress routers. Each ingress router further includes a queue for time division multiplex traffic, and at times when such traffic exists, the control unit overrides the arbitration process to allow the time division multiplex traffic to be transmitted through the switch.

Abstract: In a data switching system, the ingress and egress ports of a memoryless cross-bar switch are controlled by an arbitration method. The arbitration method uses a three phase process involving (i) a request phase in which each ingress port sends its connection requests to egress ports to which a connection is required, (ii) a grant phase in which each egress port uses a grant pointer to select one of the requests directed to it using a grant pointer, and generates a grant signal, and (iii) an accept phase in which each ingress port selects one of the received grant signals to accept, so defining an ingress to egress port connection across the cross-bar switch. The transition sequences for each of the grant pointers are mutually exclusive, so that any synchronisation of the grant pointers is eliminated on the next arbitration cycle. This is arranged by a setting of the paths taken by request and grant signals.