Abstract: A method, non-transitory computer readable medium and apparatus for correcting a timestamp in a multi-lane communication link with a skew are disclosed. For example, the method receives a data packet, a time stamp for the data packet and a fill level for a lane of the multi-lane communication link carrying the data packet, calculates a corrected timestamp for the data packet and replaces the time stamp for the data packet with the corrected timestamp.

Abstract: A method and a TDM digital switch are provided for switching data at a variety of data rates. Input streams having a data rate less than the maximum data rate of the switch are grouped and multiplexed to form multiplexed streams carrying data at the maximum data rate. A switching state machine switches the data from each input stream to form grouped output streams comprising multiplexed output streams, each grouped output stream carrying data at the maximum data rate. The grouped output streams are demultiplexed, and the output streams transmitted through respective output shift registers. The method and TDM digital switch allow streams with programmable data rates to be switched while still maximizing use of resources, including memory, within the switch.

Abstract: A time division multiplex switch supporting multi-rate input and output serial data streams has a double-buffered data memory with buffer extensions associated respectively with each portion of the memory. The extensions store residual data for a delay period after the main portion of the double-buffered data memory has switched.

Abstract: A time division multiplex switch supporting multi-rate input and output serial data streams has a double-buffered data memory with buffer extensions associated respectively with each portion of the memory. The extensions store residual data for a delay period after the main portion of the double-buffered data memory has switched.

Abstract: The present invention relates to a system for synchronising slave and master timing, comprising a phase adjust circuit for receiving and delaying an arbitrary clock signal by an adjustable amount and outputting a delayed clock signal related to the slave timing, and a master phase detector and lock circuit for comparing relative phases of the master and slave timing and in response generating and applying delay adjust signals to the phase adjust circuit at a dynamically adjusted rate which is related to the relative phase in order to synchronise the slave and master timing and is thereafter reduced to a minimum rate required to maintain synchronisation of the slave and master timing.

Abstract: A buffer memory with a memory allocation and de-allocation circuit. The buffer memory has an address space divided into address blocks and a memory address space divided into memory blocks. The circuit, in response to an allocation request for an allocation of a certain size buffer, allocates sufficient address blocks and memory blocks for the buffer. The circuit, in response to a de-allocation request to de-allocate a certain size of memory, de-allocates whole unused address blocks and memory blocks.

Abstract: A method and a TDM digital switch are provided for switching data at a variety of data rates. Input streams having a data rate less than the maximum data rate of the switch are grouped and multiplexed to form multiplexed streams carrying data at the maximum data rate. A switching state machine switches the data from each input stream to form grouped output streams comprising multiplexed output streams, each grouped output stream carrying data at the maximum data rate. The grouped output streams are demultiplexed, and the output streams transmitted through respective output shift registers. The method and TDM digital switch allow streams with programmable data rates to be switched while still maximizing use of resources, including memory, within the switch.

Abstract: An event detector for detecting a plurality of different possible asynchronous events from any of a plurality of source addresses and nodes, debouncing the events and, once a valid event has been identified and confirmed, formatting and transmitting a message via a message transport system to a predetermined destination address for further appropriate action. According to the preferred embodiment, each event is time-stamped so that latency in the message transport system does not affect time-critical events. Thus, the transmitted message identifies the source address, source node, an event number for identifying the event, and a time-stamp associated with the event.

Abstract: A buffer memory with a memory allocation and de-allocation circuit. The buffer memory has an address space divided into address blocks and a memory address space divided into memory blocks. The circuit, in response to an allocation request for an allocation of a certain size buffer, allocates sufficient address blocks and memory blocks for the buffer. The circuit, in response to a de-allocation request to de-allocate a certain size of memory, de-allocates whole unused address blocks and memory blocks.

Abstract: A switching system for switching data with rate conversion between a high speed bus and a low speed bus, comprising a double-buffered data memory having a read-only port and a write-only port, a plurality of registers and selectors for receiving and storing successive frames of data from one of either the high speed bus or low speed bus into the data memory via one of the write-only port or said read-only port, respectively; and a connection memory containing a plurality of entries each having a first bit indicating channel ON/OFF status, an additional plurality of bits identifying connection addresses for the received frames of data; and a further plurality of index bits for addressing and reading the data memory via the other one of the write-only port or read-only port in the event the first bit is set and thereafter outputting the data to the other one of the high speed bus or low speed bus.

Abstract: The present invention relates to a system for synchronising slave and master timing, comprising a phase adjust circuit for receiving and delaying an arbitrary clock signal by an adjustable amount and outputting a delayed clock signal related to the slave timing, and a master phase detector and lock circuit for comparing relative phases of the master and slave timing and in response generating and applying delay adjust signals to the phase adjust circuit at a dynamically adjusted rate which is related to the relative phase in order to synchronise the slave and master timing and is thereafter reduced to a minimum rate required to maintain synchronisation of the slave and master timing.

Abstract: A digital signal processor (DSP) interface comprised of a memory containing a pair of memory banks, apparatus for storing an input signal in a first one of the memory banks, apparatus for storing a signal from the DSP in a second one of the memory banks, apparatus for switching the content of the two memory banks, apparatus for reading either or both of the two memory banks to a first and a second memory output respectively, whereby the input signal modified or replaced by the signal from the DSP is output from the memory.