Abstract: An interrupt steering architecture that enables an intelligent peripheral device to process interrupts from PCI devices associated with a PCI bus is disclosed. The interrupt steering architecture enables the PCI interrupt signals to be steered to either a host CPU or to an intelligent peripheral device. The interrupt steering architecture is wholly compliant with the PCI bus specification and does not utilize additional sideband signals. The interrupt steering architecture is under user control and can be set by the user at system initialization or reset.

Abstract: A graphic control system under the control of a host processor to display, on a display monitor, high resolution color graphic images. The graphic control system employs a plurality of graphic display controllers each accessing, in parallel, a separate bit map storage area or a plane. When a gray-scale or color display is required, respective planes are read out in parallel and converted for serial transmission with respective outputs being supplied in parallel as a code to a look-up table of color or gray-scale codes that in turn are supplied to a digital-to-analog converter that drives the display monitor. In addition, a compare circuit is provided to receive outputs sent from the respective bit plane stores for comparison with preset outputs from the host computer to determine when the display monitor has reached a boundary of a figure being filled with a particular color or pattern.

Abstract: A digital video display system wherein the various characters to be displayed are displayed in the form of images of the complete character rather than the standard dot-matrix pattern of the prior art. A character generator in the display system stores signals representing the various characters to be displayed which are retrieved from storage in response to a character code. The signals are in the form of a binary code having a sufficient number of bits to represent a different number of levels of gray-scale or luminance values for the various picture elements making up the character image. The binary codes thus retrieved from storage are supplied to a video synthesizer that generates the video signal to display the character images which may be displayed in a number of different modes including white-on-black, black-on-white, black-on-gray, and white-on-gray as well as different combinations of such modes to represent a cursor.

Abstract: This disclosure relates to a video output circuit for high resolution character generation in a digital display unit. This output circuitry includes both character generation circuits and logic circuits, the latter of which fills in information bit areas adjacent to character bit areas which form a diagonal so as thereby to round out the character being displayed. In addition, the circuitry is adapted to change the position of such characters on the display screen so as to provide superscripts and subscripts as well as provide characters which are higher and wider than the normal character display. In order to minimize time lags in the generation display of such characters, the output circuitry is provided with a series of registers so that the character generation can be received in a sequential or pipelined manner.

Abstract: This disclosure relates to a digital video display system wherein a control element is provided that includes position and count registers to specify the initial position of a scan line and the number of scan lines displayed which registers are supplied with incoming data to specify the position of each character line so that the position of a character image on display can be adjusted upwardly or downwardly to give the appearance of smooth scrolling.The various characters to be displayed are displayed in the form of images of the complete character rather than the standard dot-matrix pattern of the prior art. A character generator in the display system stores signals representing the various characters to be displayed which are retrieved from storage in response to a character code. The signals are in the form of a binary code having a sufficient number of bits to represent a different number of levels of gray-scale or luminance values for the various picture elements making up the character image.

Abstract: This disclosure relates to a digital video display system wherein the various characters to be displayed are displayed in the form of images of the complete character rather than the standard dot-matrix pattern of the prior art. A character generator in the display system stores signals representing the various characters to be displayed which are retrieved from storage in response to a character code. The signals are in the form of a binary code having a sufficient number of bits to represent a different number of levels of gray-scale or luminance values for the various picture elements making up the character image. The binary codes thus retrieved from storage are supplied to a video synthesizer that generates the video signal to display the character images which may be displayed in a number of different modes including white-on-black, black-on-white, black-on-gray, and white-on-gray as well as different combinations of such modes to represent a cursor.

Abstract: The disclosure relates to a digital display system including a display monitor and character generation circuitry to create characters on the display screen in the form of a dot matrix during the scanning of the display screen. The display screen is actually scanned twice with each field of scan being controlled by the same sets of signals from the character generator. Logic circuitry is provided between the character generator and the display screen to fill in information bit areas adjacent to character dot areas which form a diagonal so as to thereby give the displayed character a smooth appearance.