Abstract: A microfabrication device is provided. The microfabrication device includes a transistor plane formed on a substrate, the transistor plane including a plurality of field effect transistors; fluidic passages formed within the transistor plane; a dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the transistor plane.

Abstract: A transistor in an integrated circuit (IC) die includes source and drain terminals having a bulk material enclosed by a liner material. A nanoribbon channel region couples the source and drain terminals. The nanoribbon may include a transition metal and a chalcogen. The liner material may contact ends and upper and lower surfaces of the nanoribbon. The transistor may be in an interconnect layer. The source and drain terminals may be formed by conformally depositing the liner material over the ends of the nanoribbon and in voids opened in the IC die.

Abstract: A semiconductor device includes a first device plane over a substrate. The first device plane includes a first transistor device having a first source/drain (S/D) region formed in an S/D channel. A second device plane is formed over the first device plane. The second device plane includes a second transistor device having a second gate formed in a gate channel which is adjacent to the S/D channel. A first inter-level connection is formed from the first S/D region of the first transistor device to the second gate of the second transistor device. The first inter-level connection includes a lateral offset from the S/D channel to the gate channel.

Abstract: A semiconductor device includes a device plane including an array of cells each including a transistor device. The device plane is formed on a working surface of a substrate and has a front side and a backside opposite the front side. A signal wiring structure is formed on the front side of the device plane. A front-side power distribution network (FSPDN) is positioned on the front side of the device plane. A buried power rail (BPR) is disposed below the device plane on the backside of the device plane. A power tap structure is formed in the device plane. The power tap structure electrically connects the BPR to the FSPDN and electrically connects the BPR to at least one of the transistor devices to provide power to the at least one of the transistor devices.

Abstract: A semiconductor device includes a cell array having tracks and rows formed on a substrate. The tracks extend perpendicularly to the rows. A logic cell is formed across two adjacent rows within the cell array. The logic cell includes a cross-couple (XC) in each row and a plurality of poly tracks across the two adjacent rows. Each XC includes two cross-coupled complementary field-effect-transistors. Each poly track is configured to function as an inter-row gate for the XCs. A pair of signal tracks is positioned on opposing boundaries of the logic cell and electrically coupled to the plurality of poly tracks.

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first power delivery network (PDN) structure, and a first semiconductor device tier disposed over and electrically connected to the first PDN structure. The multi-tier semiconductor structure can further include a signal wiring tier disposed over and electrically connected to the first semiconductor device tier, a second semiconductor device tier disposed over and electrically connected to the signal wiring tier, and a second PDN structure disposed over and electrically connected to the second semiconductor device tier. The multi-tier semiconductor structure can further include a through-silicon via (TSV) structure electrically connected to the signal wiring tier, wherein the TSV structure penetrates the second PDN structure.

Abstract: Techniques herein include methods for fabricating CFET devices. The methods enable high-temperature processes to be performed for FINFET and gate all around (GAA) technologies without degradation of temperature sensitive materials within the device and transistors. In particular, high temperature anneals and depositions can be performed prior to deposition of temperature-sensitive materials, such as work function metals and silicides. The methods enable at least two transistor devices to be fabricated in a stepwise manner while preventing thermal violations of any materials in either transistor.

Abstract: A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor.

Abstract: In a semiconductor device, a first stack is positioned over substrate and includes a first pair of transistors and a second pair of transistors stacked over the substrate. A second stack is positioned over the substrate and adjacent to the first stack. The second stack includes a third pair of transistors and a fourth pair of transistors stacked over the substrate. A first capacitor is stacked with the first and second stacks. A second capacitor is positioned adjacent to the first capacitor and stacked with the first and second stacks. A first group of the transistors in the first and second stacks is coupled to each other to form a static random-access memory cell. A second group of the transistors in the first and second stacks is coupled to the first and second capacitors to form a first dynamic random-access memory (DRAM) cell and a second DRAM cell.

Abstract: A semiconductor device includes a first three dimensional (3D) transistor and a second 3D transistor oriented parallel to the first 3D transistor disposed in a substrate, the first 3D transistor and the second 3D transistor being a subset of a plurality of transistors. The device includes a diffusion-break trench disposed in a region laterally separating the second 3D transistor from the first 3D transistor, the diffusion-break trench having a length extending along a lateral direction. The device includes a diffusion-break wire filling the diffusion-break trench, the diffusion-break wire having a height along a vertical direction, gates of the plurality of transistors being made of a different conductive material than the diffusion-break wire.

Abstract: A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor.

Abstract: Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower channel structure, an upper channel structure formed vertically over the lower channel, a first transistor device including lower and upper gates formed around a first portion of the lower and upper channel structures, respectively, and a separation layer formed between and separating the lower and upper gates, and a second transistor device including a common gate formed around a second portion of the lower and upper channel structures. The first portion of the lower channel structure is equal to the first portion of the upper channel structure in width, and has a first width less than a second width of the second portion of the lower channel structure.

Abstract: A microfabrication device is provided. The microfabrication device includes a combined substrate including a first substrate connected to a second substrate, the first substrate having first devices and the second substrate having second devices; fluidic passages formed at a connection point between the first substrate and the second substrate, the connection point including a wiring structure that electrically connects first devices to second devices and physically connects the first substrate to the second substrate; dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the fluidic passages to transfer heat.

Abstract: Aspects of the present disclosure provide a self-aligned microfabrication method, which can include providing a substrate having vertically arranged first and second channel structures, forming first and second sacrificial contacts to cover ends of the first and second channel structures, respectively, covering the first and second sacrificial contacts with a fill material, recessing the fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered, replacing the second sacrificial contact with a cover spacer, removing a remaining portion of the first fill material, uncovering the end of the first channel structure, forming a first source/drain (S/D) contact to cover the end of the first channel structure, covering the first S/D contact with a second fill material, uncovering the end of the second channel structure, and forming a second S/D contact at the end of the second channel structure.

Abstract: Aspects of the present disclosure provide a method of manufacturing a three-dimensional (3D) semiconductor device. For example, the method can include forming a target structure, the target structure including a lower gate region, an upper gate region, and a separation layer disposed between and separating the lower gate region and the upper gate region. The method can also include forming a sacrificial contact structure extending vertically from the bottom gate region through the separation layer and the upper gate region to a position above the upper gate region, removing at least a portion of the sacrificial contact structure resulting in a lower gate contact opening extending from the position above the upper gate region to the bottom gate region, insulating a side wall surface of the lower gate contact opening, and filling the lower gate contact opening with a conductor to form a lower gate contact.

Abstract: Aspects of the present disclosure provide a method, which includes providing a semiconductor structure including a first lower semiconductor device and a first upper semiconductor device stacked vertically over the first lower semiconductor device. The first lower semiconductor device has one or more first lower channels. The first upper semiconductor device has one or more first upper channels. First work function metal (WFM) can cover the first lower channels and the first upper channels. The method can also include recessing the first WFM to uncover the first upper channels of the first upper semiconductor device, depositing a monolayer on uncovered dielectric surfaces of the semiconductor structure, depositing isolation dielectric on the first WFM of the first lower semiconductor device, and depositing second WFM to cover the first upper channels of the first upper semiconductor device. The isolation dielectric isolates the first lower semiconductor device from the first upper semiconductor device.

Abstract: A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor.

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the semiconductor structure can include a lower semiconductor device tier including lower semiconductor devices, an upper semiconductor device tier disposed over the lower semiconductor device tier and including upper semiconductor devices, a separation layer disposed between and separating the lower and upper semiconductor device tiers, a wiring tier disposed below the lower semiconductor device tier, a lower gate contact extending from a lower gate region of the lower semiconductor device tier downward to the wiring tier, an upper gate contact extending from an upper gate region of the upper semiconductor device tier downward through the separation layer to the wiring tier, and an isolator covering a lateral surface of the upper gate contact and electrically isolating the upper and lower gate contacts. The lower gate contact and the upper gate contact can be independent from each other.

Abstract: In a semiconductor device, a first stack is positioned over substrate and includes a first pair of transistors and a second pair of transistors stacked over the substrate. A second stack is positioned over the substrate and adjacent to the first stack. The second stack includes a third pair of transistors and a fourth pair of transistors stacked over the substrate. A first capacitor is stacked with the first and second stacks. A second capacitor is positioned adjacent to the first capacitor and stacked with the first and second stacks. A first group of the transistors in the first and second stacks is coupled to each other to form a static random-access memory cell. A second group of the transistors in the first and second stacks is coupled to the first and second capacitors to form a first dynamic random-access memory (DRAM) cell and a second DRAM cell.

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first semiconductor device tier that includes first semiconductor devices. A first signal wiring structure can be formed over and electrically connected to the first semiconductor device tier. An insulator layer can be formed over the first signal wiring structure. A second semiconductor device tier can be formed over the insulator layer, the second semiconductor device tier including second semiconductor devices. A second signal wiring structure can be formed over and electrically connected to the second semiconductor device tier. An inter-tier via can be formed vertically through the insulator layer and electrically connecting the second signal wiring structure to the first signal wiring structure. The first semiconductor device tier, the second semiconductor device tier and the inter-tier via can be formed monolithically.