Patents by Inventor Paul H. Bardell, Jr.

Paul H. Bardell, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5442640
    Abstract: This invention addresses the testing and diagnosis of failures in the post-logic of products having embedded arrays. The post-logic is the combinational logic that is fed by the embedded array. Since there is no direct access to the post-logic (no direct controllability) it requires special handling. The testing method comprises initializing the array to random values; choosing an address from the array; reading out the information from that address, while applying random signals at the primary inputs. This process is continued for a predetermined number of cycles, while holding that address and applying different random signals at the primary inputs. The process is then repeated while choosing different addresses from the array. Fault diagnosis is accomplished by means of a notebook that retains the past history of the addresses chosen from the array.
    Type: Grant
    Filed: December 7, 1994
    Date of Patent: August 15, 1995
    Assignee: International Business Machines Corporation
    Inventors: Paul H. Bardell, Jr., Jacob Savir
  • Patent number: 5150366
    Abstract: Delays in critical signal paths are eliminated in circuits employing level sensitive scan design methods for implementing self-test operations. In particular, scan strings associataed with primary input lines are segregated and supplied to a separate distinct signature register so as to permit simplified degating circuitry on the input side of those shift register latches which are in fact associated with primary input signal lines.
    Type: Grant
    Filed: August 1, 1990
    Date of Patent: September 22, 1992
    Assignee: International Business Machines Corp.
    Inventors: Paul H. Bardell, Jr., William H. McAnney
  • Patent number: 4959832
    Abstract: Phase enhancement means are employed in conjunction with linear feedback shift registers to generate sequences of binary pattern vectors which are much more structurally independent of one another thus enabling more thorough and comprehensive testing of integrated circuit systems. More particularly, the present invention employs a plurality of exclusive-OR gates in an array of one gate per register output cell to generate the desired uncorrelated pattern strings. This facilitates testing of integrated circuit devices and systems and is particularly useful for built-in test situations for very large scale integrated circuits which employ pseudorandom test methods.
    Type: Grant
    Filed: December 9, 1988
    Date of Patent: September 25, 1990
    Assignee: International Business Machines
    Inventor: Paul H. Bardell, Jr.
  • Patent number: 4513418
    Abstract: The LSSD scan paths on a number of logic circuit chips are modified and connected together in series to simultaneously serve as a random signal generator and data compression circuit to perform random stimuli signature generation.
    Type: Grant
    Filed: November 8, 1982
    Date of Patent: April 23, 1985
    Assignee: International Business Machines Corporation
    Inventors: Paul H. Bardell, Jr., William H. McAnney