Abstract: A PHY entity for a UWB system utilizes the unlicensed 3.1-10.6 GHZ UWB band, as regulated in the United States by the Code of Federal Regulation, Title 47, Section 15. The UWB system provides a wireless pico area network (PAN) with data payload communication capabilities of 55, 80, 110, 160, 200, 320 and 480 Mb/s. The UWB system employs orthogonal frequency division multiplexing (OFDM) and uses a total of 122 sub-carriers that are modulated using quadrature phase shift keying (QPSK). Forward error correction coding (convolutional coding) is used with a coding rate of 11/32, 1/2, 5/8 and 3/4.

Abstract: Methods and apparatus to detect an over-current in switching circuits are described. An example method to detect an over-current in a switching circuit includes randomly selecting a sensor from a plurality of sensors operatively coupled to an output stage of the switching circuit; detecting a first voltage via the randomly selected sensor; and comparing the first voltage to a reference voltage to generate a signal, wherein the signal indicates a status of the output stage of the switching circuit.

Abstract: System for ultra-wideband communications providing high data rates over an extended operating range in the presence of interferers. A preferred embodiment comprises an ultra-wideband (UWB) device that makes use of a portion of the UWB frequency range to help provide good performance in the presence of interferers. Additionally, since only a portion of the UWB frequency range is used, multiple devices can simultaneously transmit and receive by using different portions of the UWB frequency range.

Abstract: A sample-and-hold (SAH) phase detector (PD) is clocked in such a way (using a reverse clocking mode) so as to avoid quantization noise increases due to folding that is generally associated with conventional charge pump based phase detectors. The PD is clocked with a clean clock (reference clock), rather than a divided clock. The SAH PD architecture additionally includes an integrated filtering function.

Abstract: Multi-mode class-D amplifiers are disclosed. An example multi-mode class-D amplifier circuit having an analog input and a digital input disclosed herein comprises a single-mode class-D amplifier having an amplifier input, a smoothing filter having a filter input and a filter output, wherein the filter output is electronically coupled to the amplifier input, and a multiplexer electronically coupled to the filter input to select between at least one of the analog input and the digital input of the multi-mode class-D amplifier circuit.

Abstract: A receiver 100 is provided. The receiver 100 comprises an in-phase analog-to-digital converter 112 operable to detect a saturation condition of the in-phase analog-to-digital converter 112 and to adjust the amplitude of a in-phase signal processed by the in-phase analog-to-digital converter 112 to remove the in-phase analog-to-digital converter 112 from the saturation condition and a in-phase digital filter 114 operable to adjust a gain applied to a digital input to the in-phase digital filter 114 from the in-phase analog-to-digital converter 112, the adjustment of the gain substantially inversely proportional to the adjustment of the amplitude of the in-phase signal processed by the in-phase analog-to-digital converter 112. In an embodiment, the receiver 100 also comprises a quadrature path that is substantially similar to the in-phase path, and the in-phase path and the quadrature path comprise a direct conversion receiver.

Abstract: The present invention provides a system for providing high-resolution calibration of a programmable semiconductor component (518). The system calibrates the programmable semiconductor component, within a desired accuracy, to a goal value (802). The system provides a primary DAC function (510) and a supplemental DAC function (512), as well as a control function (506). The control function is utilized to determine a first bit step (806) of the primary DAC function that corresponds to the goal value. The control function then determines a second bit step (810) of the supplemental DAC function that corresponds to the goal value. The bit codes of the first and second bit steps are combined by a summing function (514), to provide a programming control word for the programmable semiconductor component.

Abstract: A technique is provided for achieving efficient modulation compensation of a &Sgr;&Dgr; fractional PLL. The parameters of the PLL TF are the gain, Kpll, of the PLL and the time constants associated with the loop filter. A careful design of the PLL allows setting the poles and zeros of the PLL TF to fixed values, independent of process and temperature. The unknown parameters of the system are then reduced to one: the PLL gain, K which is the product of the Voltage Controlled Oscillator (VCO), Phase Detector (PD) and divider gains. One unknown variable can be then determined via a single equation, that can be derived at a single frequency. The measurement of a low frequency modulated single tone, for example, is sufficient to characterize the entire PLL TF.

Abstract: A technique is provided for achieving efficient modulation compensation of a &Sgr;&Dgr; fractional PLL. The parameters of the PLL TF are the gain, Kpll, of the PLL and the time constants associated with the loop filter. A careful design of the PLL allows setting the poles and zeros of the PLL TF to fixed values, independent of process and temperature. The unknown parameters of the system are then reduced to one: the PLL gain, K which is the product of the Voltage Controlled Oscillator (VCO), Phase Detector (PD) and divider gains. One unknown variable can be then determined via a single equation, that can be derived at a single frequency. The measurement of a low frequency modulated single tone, for example, is sufficient to characterize the entire PLL TF.

Abstract: A PHY entity for a UWB system utilizes the unlicensed 3.1-10.6 GHZ UWB band, as regulated in the United States by the Code of Federal Regulation, Title 47, Section 15. The UWB system provides a wireless pico area network (PAN) with data payload communication capabilities of 55, 80, 110, 160, 200, 320 and 480 Mb/s. The UWB system employs orthogonal frequency division multiplexing (OFDM) and uses a total of 122 sub-carriers that are modulated using quadrature phase shift keying (QPSK). Forward error correction coding (convolutional coding) is used with a coding rate of {fraction (11/32)}, ½, ⅝ and ¾.

Abstract: System for ultra-wideband communications providing high data rates over an extended operating range in the presence of interferers. A preferred embodiment comprises an ultra-wideband (UWB) device that makes use of a portion of the UWB frequency range to help provide good performance in the presence of interferers. Additionally, since only a portion of the UWB frequency range is used, multiple devices can simultaneously transmit and receive by using different portions of the UWB frequency range.

Abstract: A wireless telephone (40) is disclosed, in which audio input/output circuitry (44) includes a digital-to-analog conversion function (50) for producing an analog output signal (s(t)) based upon a digital baseband signal (S) from a digital signal processor (42). The digital-to-analog conversion function (50) includes first and second &Sgr;&Dgr; modulators (46, 48), each of which are controlled by a sampling clock generated by a dual frequency divider (47) controlled by the first &Sgr;&Dgr; modulator (46). A sampling latch (49) samples the digital baseband signal synchronously with the sampling clock. The second &Sgr;&Dgr; modulator (48) selects an oversampling multiple that is applied to a digit filter (52) along with the sampled signal from the sampling latch (49). The digital filter (52) reconstructs a digital signal from the sampled value and the oversampling multiple that is the equivalent of that reconstructed by the decimation of an over sampled signal.