Abstract: A plurality of varactors are coupled via a first electrode to a shared terminal that in turn can operably couple to a source of control voltage. A second electrode for each varactor couples to a corresponding switch, where each switch couples to at least two different voltage levels. So configured, the second electrode of each varactor can be individually connected to either of two voltage levels. This can be leveraged to control, in coarse steps, the overall aggregate effective capacitance presented by these components. At least some of these varactors can have differing corresponding capacitances, the specific values of which can be selected in order to facilitate relatively equal spacing and substantially equal rates of reactance change versus the control voltage value between aggregate-capacitive reactance ranges as correspond to differing settings for the switches at various levels for the control voltage source.

Abstract: A DPC (200) that includes: a frequency source (20); a delay-locked loop (220) for receiving a clock signal and generating a plurality of phase-shifted clock signals; a control device (280) having a DPS (282) and a DAC (284) for receiving an input signal identifying a desired frequency for a synthesized signal; a selection circuit (270) for receiving the plurality of phase-shifted clock signals, selecting a sequence of the phase-shifted clock signals and outputting a coarse synthesized signal; a variable delay cell (290) having a first input coupled to the selection circuit to receive the coarse synthesized signal and a second input coupled to the control device for receiving a fine tune adjustment signal to modify the coarse synthesized signal to generate the synthesized signal (292) having substantially the desired frequency. The DPC further includes training apparatus for calibrating the DPC.

Abstract: A delay-locked loop 300 that includes: an adjustable frequency source (320) for generating a clock signal (322) having an adjustable frequency; an adjustment and tap selection controller (310) for determining a first frequency as a function of a second frequency and for causing the frequency source to adjust the frequency of the clock signal to substantially the first frequency, the second frequency being the desired frequency of a first output signal; a delay line (330) configured to receive the clock signal for generating a plurality of phase-shifted clock signals; and a first selection circuit (370) for receiving the plurality of phase-shifted clock signals and for selecting, one at a time and under the control of the adjustment and tap selection controller, a first sequence of the phase-shifted clock signals for generating the first output signal having substantially the second frequency.

Abstract: A power amplifier that includes: an input drive controller (310) for receiving an input signal (312) and for generating from the input signal at least a first drive signal (314), a second drive signal (316), and a third drive signal (318); an outphasing amplifier network (320) coupled to the input drive controller that includes at least a first outphasing amplifier (322) for amplifying the first drive signal and a second outphasing amplifier (326) for amplifying the second drive signal; a peaking amplifier network (330) coupled to the input drive controller that includes at least a first peaking amplifier (332) for amplifying the third drive signal; and a combining network (340) coupled to the outphasing amplifier network and the peaking amplifier network for combining at least the amplified first, second and third drive signals to generate an output signal at a load.

Abstract: A linear transmitter includes an amplifier feedback loop for amplifying an input signal at a power amplifier. The feedback loop is operated in an open loop mode when the power amplifier is operating at a first operating point and is operated in a closed loop mode when the power amplifier is operating at a second operating point. The transmitter further includes an auxiliary loop coupled to the amplifier feedback loop that provides phase training for the feedback loop and power leveling when the feedback loop is operating open loop. Open loop phase training and power leveling is done during open loop transmission, without an associated training signal or training period. Stable closed loop operation can commence subsequently providing the higher power amplifier efficiency associated with the second operating point and maintaining off channel interference requirements.

Abstract: A feedback loop with an adjustable closed loop frequency response. The feedback loop contains adjustable pole (212, 213) and adjustable zero elements (220,221) for changing the pole and/or zero locations in the feedback loop's loop frequency response thereby changing the closed loop frequency response of the feedback loop. In one embodiment, the feedback loop is a Cartesian feedback loop suitable for use in a radio transmitter.

Abstract: A method and apparatus is provided that amplitude modulates a modulated radio frequency (RF) signal (411) by modulating the supply voltage of a power amplifier (410). The method and apparatus further provides an impedance modulator (412) that reduces output signal (415) errors in response to an error signal generated by a feedback circuit (416) that includes a quadrature modulator (506), a limiter (520), a comparator (502), and a quadrature downconverter (510). Intermodulation distortion generated in the feedback circuit (416) by delay mismatches between amplitude and phase feedback paths, and non-linear effects of AM/PM conversion in a limiter (520), are suppressed by placing limiter (520) and quadrature downconverter (510) in a forward path of the overall amplifier loop.

Abstract: An integrated sigma-delta radio frequency (RF) receiver subsystem (200) and method utilizes a multi-mode sigma-delta analog-to-digital converter (215) for providing a single and multi-bit output. A programmable decimation network (221) for reducing the frequency of the in-phase and quadrature bit stream and a programmable formatting network (223) are also used for organizing the in-phase and quadrature components from the decimation network (221) for subsequent signal processing. The invention offers a highly integrated digital/analog RF receiver back-end which incorporates integrated filtering and a smart gain control that is compatible for use with other receiver systems and offering superior performance characteristics.

Abstract: An apparatus includes a current generator (101) having an output. A plurality of mixers (103, 105, and 107) is switchably coupled to the current generator output, such that a first average power output level is provided when a first mixer (103) of the plurality of mixers is engaged and a second average power output level is provided when a second mixer (105) of the plurality of mixers is engaged. Alternatively, a first average power output level is provided when a first mixer (103) and a second mixer (105) of the plurality of mixers is engaged and a second average power output level is provided when the first mixer (103) of the plurality of mixers is engaged. The first average power output level and the second average power output level are different.

Abstract: An apparatus and method produce a plurality of output signals (917-921) with fixed phase relationships therebetween. The apparatus (900) includes a first signal generator (901), a second signal generator (903), and a signal processor (907). The first signal generator produces a first input signal (911) at a first frequency. The second signal generator produces a second input signal (915) at a second frequency, wherein the second frequency is an integer multiple of the first frequency. The signal processor receives the first and second input signals and produces a plurality of output signals (917-921) having fixed phase relationships therebetween at the first frequency, wherein the fixed phase relationships are based on the integer multiple and wherein each of the output signals has a single, determinate phase relative to the phase of the first input signal.

Abstract: An integrated multi-mode bandpass sigma-delta radio frequency receiver subsystem with interference mitigation includes a first intermediate frequency amplifier. At least one mixer for mixing the output of the first amplifier and an oscillator signal. A second IF amplifier for amplifying and filtering the output of the at least one mixer. A multi mode multi bandwidth sigma delta analog digital converter for providing digital output signals with high dynamic range. A digital mixer providing I and Q signals a decimation network providing I and Q signals at reduced programmable data and clock frequencies and a formatting network for arranging the I and Q signals into a predetermined format for use with a digital signal processor.

Abstract: An apparatus includes a current generator (101) having an output. A plurality of mixers (103, 105, and 107) is switchably coupled to the current generator output, such that a first average power output level is provided when a first mixer (103) of the plurality of mixers is engaged and a second average power output level is provided when a second mixer (105) of the plurality of mixers is engaged. The first average power output level and the second average power output level are different.

Abstract: An apparatus and method produce a plurality of output signals (917-921) with fixed phase relationships therebetween. The apparatus (900) includes a first signal generator (901), a second signal generator (903), and a signal processor (907). The first signal generator produces a first input signal (911) at a first frequency. The second signal generator produces a second input signal (915) at a second frequency, wherein the second frequency is an integer multiple of the first frequency. The signal processor receives the first and second input signals and produces a plurality of output signals (917-921) having fixed phase relationships therebetween at the first frequency, wherein the fixed phase relationships are based on the integer multiple and wherein each of the output signals has a single, determinate phase relative to the phase of the first input signal.

Abstract: An amplifier structure (200) includes a main amplifier loop (203) for efficiently amplifying an input signal at a power amplifier (228) coupled to a load susceptible to impedance variations. The amplifier structure (200) includes a DC correction circuit (214) for detecting and correcting misadjustments in the amplifier (200) in order to eliminate DC offset associated therewith.

Abstract: An amplifier structure (200) includes a main amplifier loop (203) for efficiently amplifying an input signal at a power amplifier (228) coupled to a load susceptible to impedance variations. The amplifier loop (200) further includes an auxiliary loop (201) coupled to the main loop (201) for simultaneously preventing the power amplifier (228) from operating inefficiently or causing off-channel interference.

Abstract: A zero-IF transmitter (200) has a DC offset, representative of a carrier feedthrough signal. A value to correct the DC offset is successively approximated (207). A summer (201) adds the value to a desired input to reduce the DC offset.

Abstract: A linear transmitter (100), which utilizes closed loop feedback to maintain its linearity, employs a method for reducing off-channel interference produced by the linear transmitter (100). A dynamically alterable parameter source (DAPS, 126) is provided to the linear transmitter (100). The DAPS (126) is then used to adjust at least one loop parameter of the closed loop feedback such that off-channel interference is reduced.

Abstract: In a radio transmitter (100) that includes a power amplifier (104) and an antenna (106), a method for enhancing an operating characteristic of the radio transmitter (100) can be accomplished in the following manner. The power amplifier (104) provides a signal (113) to a variable matching network (111), wherein the signal (113) comprises energy to be radiated by the antenna (106). The variable matching network (111) couples the signal (113) to a sampler (112) that is operably coupled to an output of the variable matching network (111 ) and the antenna (106). The sampler (112) samples a forward component (114) and a reflected component (115) of the signal (113). The radio transmitter (100) processes the sampled forward and reflected components (116, 118) to produce a feedback control signal (120). The feedback control signal (120) is used to adjust the variable matching network (111 ), such that an operating characteristic of the radio transmitter (100) is enhanced.

Abstract: A method and apparatus is provided for a transmitter (200) with a stable, linear response. The transmitter (200) includes an amplification stage (242), and a negative feedback correction loop (244) with a feedback signal (252). A reference signal (251) is combined with the feedback signal (252) to produce an error signal (253) for coupling to the amplification stage (242). Transmitter parameters are varied when a difference between the reference signal (251) and the error signal (253) exceeds a particular threshold.

Abstract: A linear amplifier (103) has a negative feedback loop that has a closed loop gain and a forward path gain. The negative feedback loop is closed, such that quick changes in the closed loop gain are prevented, thereby reducing splatter. When the negative feedback loop is opened, quick changes in the closed loop gain are also prevented, thereby reducing splatter.