Abstract: In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.

Abstract: A clock signal generator responsive to synchronization pulses to perform actions has a phase locked loop (PLL) part including a digitally controlled oscillator (DCO) and an output driver coupled to the DCO, and a synthesizer part including a frequency synthesizer responsive to frequency and phase information from the DCO to generate a synthesized clock and programmable output dividers for generating output clocks from the synthesized clock. An interface establishes communication between the PLL part and the synthesizer part. The output driver is programmed to compute a phase offset required to align a selected output divider with the phase of the DCO and transmit the computed offset to the selected output divider over said interface for application to said selected output divider upon the occurrence of a synchronization pulse.

Abstract: A phase locked loop with holdover mode has a loop filter for creating an offset frequency value for a controlled oscillator. The loop filter includes a register for storing the current offset frequency value the said controlled oscillator. A first multiplexer responsive to a holdover signal selects, depending on the quality of a reference signal, the output of the loop filter or a holdover queue to control the controlled oscillator. A second multiplexer responsive to the holdover signal selects for input to the register, depending on the quality of the reference signal, the sum of an output of the register and a value derived from the current phase difference between the output of the controlled oscillator and the reference signal or a current output value of the holdover queue.

Abstract: Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating clock signals is selected to drive the DCO. The performance of the crystal oscillators is monitored, and the DCO is switched from being driven by a previously selected crystal oscillator to a newly selected crystal oscillator upon loss of a clock signal from the previously selected crystal oscillator or when the performance of the previously selected crystal oscillator falls below a predetermined acceptable level.

Abstract: A multi-channel phase locked loop (PLL) device has a plurality of PLL channels. Each channel includes a digitally controlled oscillator (DCO) supplying an output clock, via an output divider, to a respective output pin. A first multiplexer selects any of the PLL channels for alignment. A feedback calibration PLL is responsive to a feedback signal derived from an output clock of a selected channel at the respective output pin. A delay control module is responsive to an output of the feedback calibration PLL to adjust the phase of the output clock.

Abstract: A clock signal generator responsive to synchronization pulses to perform actions has a phase locked loop (PLL) part including a digitally controlled oscillator (DCO) and an output driver coupled to the DCO, and a synthesizer part including a frequency synthesizer responsive to frequency and phase information from the DCO to generate a synthesized clock and programmable output dividers for generating output clocks from the synthesized clock. An interface establishes communication between the PLL part and the synthesizer part. The output driver is programmed to compute a phase offset required to align a selected output divider with the phase of the DCO and transmit the computed offset to the selected output divider over said interface for application to said selected output divider upon the occurrence of a synchronization pulse.

Abstract: Master clock redundancy is provided for a digital phase locked loop having a digital controlled oscillator (DCO) driven by a master clock source, for example, a crystal oscillator. One of a plurality of a crystal oscillators generating clock signals is selected to drive the DCO. The performance of the crystal oscillators is monitored, and the DCO is switched from being driven by a previously selected crystal oscillator to a newly selected crystal oscillator upon loss of a clock signal from the previously selected crystal oscillator or when the performance of the previously selected crystal oscillator falls below a predetermined acceptable level.

Abstract: A multi-channel phase locked loop (PLL) device has a plurality of PLL channels. Each channel includes a digitally controlled oscillator (DCO) supplying an output clock, via an output divider, to a respective output pin. A first multiplexer selects any of the PLL channels for alignment. A feedback calibration PLL is responsive to a feedback signal derived from an output clock of a selected channel at the respective output pin. A delay control module is responsive to an output of the feedback calibration PLL to adjust the phase of the output clock.

Abstract: A phase locked loop with holdover mode has a loop filter for creating an offset frequency value for a controlled oscillator. The loop filter includes a register for storing the current offset frequency value the said controlled oscillator. A first multiplexer responsive to a holdover signal selects, depending on the quality of a reference signal, the output of the loop filter or a holdover queue to control the controlled oscillator. A second multiplexer responsive to the holdover signal selects for input to the register, depending on the quality of the reference signal, the sum of an output of the register and a value derived from the current phase difference between the output of the controlled oscillator and the reference signal or a current output value of the holdover queue.

Abstract: In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.

Abstract: A clock generator with glitchless phase adjustment having a phase locked loop with a controlled oscillator providing an output representing a phase value. One or more output modules generate one or more output clocks from the output. One or more adjustment modules add a requested phase adjustment to an output clock. The phase adjustment modules are configured to break the requested phase adjustment into smaller increments and apply the increments to an output clock generated in said at the output modules one cycle at a time.

Abstract: A digital phase locked loop has a phase acquisition module that outputs a first phase value representative of the phase of a reference signal expressed with respect to an internal phase reference. A phase offset write module convert a phases offset commanded from an external source into a phase offset correction value expressed with respect to the internal phase reference. A phase offset controller sums the phase offset correction values to produce a second phase value, which is added to the first phase value to produce a third phase value expressed with respect to the internal phase reference. A digital controlled oscillator (DCO) outputs a fourth phase value expressed with respect to the internal phase reference. A phase detector outputs a fifth phase value representing the difference between the third and fourth phase values. A loop filter derives a frequency offset for the DCO based on the fifth phase value. An output module generates one or more output clocks from the fourth phase value.

Abstract: A digital phase locked loop has a phase acquisition module that outputs a first phase value representative of the phase of a reference signal expressed with respect to an internal phase reference. A phase offset write module convert a phases offset commanded from an external source into a phase offset correction value expressed with respect to the internal phase reference. A phase offset controller sums the phase offset correction values to produce a second phase value, which is added to the first phase value to produce a third phase value expressed with respect to the internal phase reference. A digital controlled oscillator (DCO) outputs a fourth phase value expressed with respect to the internal phase reference. A phase detector outputs a fifth phase value representing the difference between the third and fourth phase values. A loop filter derives a frequency offset for the DCO based on the fifth phase value. An output module generates one or more output clocks from the fourth phase value.

Abstract: A clock generator with glitchless phase adjustment having a phase locked loop with a controlled oscillator providing an output representing a phase value. One or more output modules generate one or more output clocks from the output. One or more adjustment modules add a requested phase adjustment to an output clock. The phase adjustment modules are configured to break the requested phase adjustment into smaller increments and apply the increments to an output clock generated in said at the output modules one cycle at a time.