Abstract: An Array Matrix of red and infrared light emitting diodes (LED) are mounted onto to a flexible printed circuit board (FPCB) to produce a compact and wearable Low Level Light Therapy (LLLT) Device. An effective heat releasing method is employed to enable a long period of continuous use of the LLLT device.

Abstract: A circuit and a method are disclosed to provide a tristate input/output buffer which is compatible with 5 volt input signals, applied to its input/output (I/O) node, while operating with a 3 volt power supply and is resistant to CMOS latchup. The 5 volt compatibility is achieved by inserting an additional p-channel transistor in series with the existing p-channel transistor and circuitry to control the additional p-channel transistor. The control circuit is comprised of 2 transistors. The CMOS latchup resistance is provided by a N-well bias generator that changes the N-well bias to be equal to the higher of the 2 voltages, VDD or the voltage present at the I/O pad. The N-well bias generator is comprised of 3 transistors.

Abstract: The rate of discharge of the sense amplifier and bit lines in a memory circuit is controlled to simulate a boosted sense ground potential without requiring the use of a voltage regulator or precharged capacitors. The sense amplifier is electrically coupled to ground through a large transistor during a first period, which quickly discharges the sense amplifier toward ground potential to ensure a fast sense speed of the sense amplifier. During a subsequent period, the large transistor is turned off and the sense amplifier is electrically coupled to ground through a smaller transistor. The small transistor slowly discharges the sense amplifier towards ground, without reaching ground, until the active cycle is over and the discharge of the sense amplifier is terminated. By holding the sense amplifier above, but near, ground potential, the subthreshold leakage of non-selected memory cells is minimized so that the frequency of refresh may be decreased, thereby minimizing standby current.

Abstract: A dynamic impedance adjustment circuit that reduces overshoot and undershoot noise while achieving fast slew rates. The dynamic impedance adjustment circuit has an output driver for selectively driving or drawing current providing source or sink current. The dynamic impedance adjustment circuit also has an a variable impedance output driver for selectively providing a dynamic current (source or sink) for a predetermined time after transitions from a logic low level to a logic high level or from a logic high level to a low logic level in the input signal. An impedance adjustment control circuit is coupled to the variable impedance output driver for automatically detecting the transitions in the input signal and for changing the impedance of the variable impedance output driver based on the input signal, enable signal, and the output node.

Abstract: Current protection circuit has a comparator having a first terminal coupled to a reference voltage, a second terminal coupled to an output node, and an output for providing a control signal based on the inputs. Current protection circuit also has a transistor having a drain electrode coupled to a first predetermined voltage, a gate electrode, and a source electrode coupled to the output node. The transistor includes a current path between the drain electrode and the source electrode for conducting an amount of current that is dependent on the voltage applied to the gate electrode. Current protection circuit also has a fold-back circuit having a first input coupled to the output node for detecting changes in the output voltage, a second input coupled to the output of comparator for receiving the control signal, and a third input for selectively changing the voltage applied to the gate electrode based the control signal and the changes in the output voltage.

Abstract: The precharge operation of a DRAM array in a non-multiplexed address interface is controlled so that the DRAM is precharged only if there is a change in the word line address. By precharging the DRAM only when a new word line is asserted, a significant power savings may be obtained. An activity monitor compares each new word line address with the previous word line address. If the activity monitor indicates that a new word line is asserted, a timing control circuit will precharge the DRAM, including equalizing the bit lines. If the activity monitor indicates that the word line is not changed, the timing control circuit does not precharge the DRAM. The timing control circuit includes a dummy precharge circuit and initiates a dummy precharge cycle in the beginning of each new cycle for timing purposes. The timing control circuit initiates the active cycle after the dummy precharge cycle regardless of whether a new word line is asserted or not.

Abstract: An improved short-channel complementary MOS transistor structure is provided. The problems of low punch-through voltage breakdown, and "short-channel effects" are particularly addressed and solved. Accurate and precise field protection of all area surrounding the channel, source and drain regions of both the p-channel MOS transistor device and the n-channel transistor device is simply and effectively accomplished. The threshold voltage of the n-channel MOS transistor device is precisely controlled by a boron implantation.The method of manufacturing such device is disclosed.