Patents by Inventor Paul Hasler

Paul Hasler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170322222
    Abstract: The present invention relates to methods for diagnosing gestational diabetes mellitus (GDM) in a pregnant female.
    Type: Application
    Filed: December 10, 2015
    Publication date: November 9, 2017
    Inventors: Stavros GIAGLIS, Sinuhe HAHN, Olav LAPAIRE, Paul HASLER
  • Publication number: 20160061824
    Abstract: The present invention relates to methods for detecting inflammatory disorders and more particularly to methods for detecting inflammatory disorders by detecting cell-free nucleosomes in a serum sample isolated from a subject.
    Type: Application
    Filed: March 2, 2014
    Publication date: March 3, 2016
    Applicant: Universitatsspital Basel
    Inventors: Sinuhe HAHN, Paul HASLER, Stavros GIAGLIS, Chanchal Sur CHOWDHURY
  • Patent number: 8018281
    Abstract: An operational amplifier including: a differential pair of transistors coupled to a pair of input signals; and a pair of floating-gate transistors coupled to the differential pair of transistors, wherein the pair of floating-gate transistors are operable for reducing an offset voltage of the operational amplifier.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: September 13, 2011
    Assignee: Georgia Tech Research Corporation
    Inventors: Paul Hasler, Venkatesh Srinivasan, Guillermo Serrano, Jordan Gray
  • Patent number: 7965559
    Abstract: The present invention describes systems and methods for improving the programming of floating-gate transistors. An exemplary embodiment of the present invention provides a floating-gate transistor programming system including an array of floating-gate transistors and a measuring circuit comprising a logarithmic transimpedance amplifier and an analog-to-digital converter. Furthermore, the floating-gate transistor programming system includes an injecting circuit comprising a digital-to-analog converter, wherein the pulsing circuit can inject charge into each of the floating-gate transistors and the measuring circuit can measure a present charge value in one of the plurality of floating-gate transistors.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: June 21, 2011
    Assignee: Georgia Tech Research Corporation
    Inventors: Paul Hasler, Arindam Basu
  • Publication number: 20100176879
    Abstract: An operational amplifier including: a differential pair of transistors coupled to a pair of input signals; and a pair of floating-gate transistors coupled to the differential pair of transistors, wherein the pair of floating-gate transistors are operable for reducing an offset voltage of the operational amplifier.
    Type: Application
    Filed: March 22, 2010
    Publication date: July 15, 2010
    Applicant: Georgia Tech Research Center Corp.
    Inventors: Paul Hasler, Venkatesh Srinivasan, Guillermo Serrano, Jordan Gray
  • Patent number: 7714650
    Abstract: An operational amplifier including: a differential pair of transistors coupled to a pair of input signals; and a pair of floating-gate transistors coupled to the differential pair of transistors, wherein the pair of floating-gate transistors are operable for reducing an offset voltage of the operational amplifier.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: May 11, 2010
    Assignee: Georgia Tech Research Corporation
    Inventors: Paul Hasler, Venkatesh Srinivasan, Guillermo Serrano, Jordan Gray
  • Publication number: 20090323425
    Abstract: The present invention describes systems and methods for improving the programming of floating-gate transistors. An exemplary embodiment of the present invention provides a floating-gate transistor programming system including an array of floating-gate transistors and a measuring circuit comprising a logarithmic transimpedance amplifier and an analog-to-digital converter. Furthermore, the floating-gate transistor programming system includes an injecting circuit comprising a digital-to-analog converter, wherein the pulsing circuit can inject charge into each of the floating-gate transistors and the measuring circuit can measure a present charge value in one of the plurality of floating-gate transistors.
    Type: Application
    Filed: May 27, 2009
    Publication date: December 31, 2009
    Applicant: Georgia Tech Research Corporation
    Inventors: Paul Hasler, Arindam Basu
  • Patent number: 7348909
    Abstract: Disclosed herein is a reconfigurable mixed signal distributed arithmetic system including: an array of tunable voltage references operable for receiving a delayed digital input signal; a combination device in electrical communication with the array of tunable floating-gate voltage references that selectively combines an output of the array of tunable voltage references into an analog output signal; and a feedback element in electrical communication with the combination device, wherein the array of tunable voltages and the delayed digital input signal combine to perform a distributed arithmetic function and the reconfigurable mixed signal distributed arithmetic system responsively generates the analog output signal.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: March 25, 2008
    Assignee: Georgia Tech Research Corporation
    Inventors: Erhan Ozalevli, Paul Hasler, David Verl Anderson, Walter Geeshan Huang
  • Publication number: 20070244698
    Abstract: A response select null steering circuit includes a beamformer, a plurality of separate fixed filters, and a selection circuit. In response to sound signals emitted from a desired speaker and an unwanted interferer, a sum signal containing signal components of the speaker and interferer is generated, and the beamformer generates a difference signal that suppresses signal components of the speaker. Each filter provides a null in a unique direction relative to the desired speaker, and can be individually configured to suppress sound signals from an interferer in a particular direction. The selection circuit selects the filter output signal that has the least amount of signal energy as achieving the best suppression of the unwanted interferer.
    Type: Application
    Filed: April 18, 2007
    Publication date: October 18, 2007
    Inventors: Jeffery Dugger, Paul Smith, Paul Hasler, Hans Klein
  • Patent number: 7280063
    Abstract: A digital to analog converter (DAC) includes an operational amplifier and a plurality of ladder elements. Each ladder element includes an epot for providing a voltage, a capacitor, and a switch for selecting between a first voltage and a reference voltage, and for providing the first selected voltage to the first capacitor. The output of the ladder elements are coupled to the inverting input of the operational amplifier. Alternatively, the ladder elements may use tunable floating-gate resistors.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: October 9, 2007
    Assignee: Georgia Tech Research Corporation
    Inventors: Erhan Ozalevli, Paul Hasler
  • Publication number: 20070210860
    Abstract: An operational amplifier including: a differential pair of transistors coupled to a pair of input signals; and a pair of floating-gate transistors coupled to the differential pair of transistors, wherein the pair of floating-gate transistors are operable for reducing an offset voltage of the operational amplifier.
    Type: Application
    Filed: August 30, 2006
    Publication date: September 13, 2007
    Applicant: Georgia Tech Research Corp.
    Inventors: Paul Hasler, Venkatesh Srinivasan, Guillermo Serrano, Jordan Gray
  • Patent number: 7269046
    Abstract: A floating-gate transistor array and method for programming the same. The floating-gate transistor array includes a plurality of transistors having a source, drain, and floating-gate, whereby the plurality of transistors is arranged into multiple rows and columns. Each row of transistors includes a row programming switch having an output connected to each floating-gate within the row, while each column of transistors includes a column programming switch having an output connected to each drain within the column. The source of each transistor is coupled with a source line corresponding to the specific row of the transistor. The row and column programming switches are utilized to select and program a desired floating-gate transistor. In an indirect programming method, two transistors share a floating gate, such that programming a programmer transistor modifies the current of an agent transistor, which is attached to the circuit, thereby permitting run-time programming.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: September 11, 2007
    Assignee: Georgia Tech Research Corporation
    Inventors: David W. Graham, Ethan Farquhar, Jordan Gray, Christopher M. Twigg, Brian Degnan, Christal Gordon, David Abramson, Paul Hasler
  • Patent number: 7250549
    Abstract: An absorbent garment includes a front body panel having a terminal waist edge and a terminal crotch edge and a rear body panel having a terminal waist edge and a terminal crotch edge. The terminal crotch edge of the rear body panel is longitudinally spaced from and forms a gap with the terminal crotch edge of the front body panel. An absorbent insert includes first and second longitudinally spaced end portions and opposite laterally spaced side edges. The absorbent insert bridges the gap between the front and rear body panels with the first and second end portions overlying and connected to the front and rear body panels respectively. At least one of the first and second end portions of the absorbent insert is connected respectively to a corresponding one of the front and rear body panels with at least first and second adhesive regions having first and second adhesive basis weights respectively.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: July 31, 2007
    Assignee: Kimberly-Clark Worldwide, Inc.
    Inventors: Sandra A. Richlen, Paul Christoffel, Suzanne M. Schmoker, Paul Hasler, Sarah Freiburger, David F. Bishop, Melanie J. Milslagle
  • Publication number: 20070040712
    Abstract: Disclosed herein is a reconfigurable mixed signal distributed arithmetic system including: an array of tunable voltage references operable for receiving a delayed digital input signal; a combination device in electrical communication with the array of tunable floating-gate voltage references that selectively combines an output of the array of tunable voltage references into an analog output signal; and a feedback element in electrical communication with the combination device, wherein the array of tunable voltages and the delayed digital input signal combine to perform a distributed arithmetic function and the reconfigurable mixed signal distributed arithmetic system responsively generates the analog output signal.
    Type: Application
    Filed: August 17, 2006
    Publication date: February 22, 2007
    Applicant: Georgia Tech Research Corporation
    Inventors: Erhan Ozalevli, Paul Hasler, David Anderson, Walter Huang
  • Publication number: 20070007999
    Abstract: A floating-gate transistor array and method for programming the same. The floating-gate transistor array includes a plurality of transistors having a source, drain, and floating-gate, whereby the plurality of transistors is arranged into multiple rows and columns. Each row of transistors includes a row programming switch having an output connected to each floating-gate within the row, while each column of transistors includes a column programming switch having an output connected to each drain within the column. The source of each transistor is coupled with a source line corresponding to the specific row of the transistor. The row and column programming switches are utilized to select and program a desired floating-gate transistor. In an indirect programming method, two transistors share a floating gate, such that programming a programmer transistor modifies the current of an agent transistor, which is attached to the circuit, thereby permitting run-time programming.
    Type: Application
    Filed: May 10, 2006
    Publication date: January 11, 2007
    Applicant: Georgia Tech Research Corporation
    Inventors: David Graham, Ethan Farquhar, Jordan Gray, Christopher Twigg, Brian Degnan, Christal Gordon, David Abramson, Paul Hasler
  • Publication number: 20060273805
    Abstract: The present invention relates to systems and methods for sensing capacitance change of a capacitive sensor and for optimizing a capacitive sensing circuit. In an exemplary embodiment, a capacitive sensor may be coupled to an amplifier at floating node. A programming circuit is connected to the floating node for controlling a charge on the floating node. A method of controlling the charge of the floating node is also provided. The method includes applying a first predetermined voltage to a source of a programming transistor, applying a second predetermined voltage to a floating gate of the programming transistor, and applying a third predetermined voltage to a drain of the programming transistor until a charge on the floating gate of the programming transistor reaches a predetermined value. The charge on the floating gate of the programming transistor drives the charge on the floating node to the predetermined value, and thus is controlled.
    Type: Application
    Filed: June 2, 2006
    Publication date: December 7, 2006
    Applicant: Georgia Tech Research Corporation
    Inventors: Sheng-Yu Peng, Paul Hasler
  • Publication number: 20060261846
    Abstract: A large-scale field-programmable analog array (FPAA) for rapidly prototyping analog systems and an arbitrary analog waveform generator. The large-scale FPAA includes a floating-gate transistor array and a plurality of computational analog blocks (CABs), which may be adapted to set bias voltages for operational transconductance amplifiers (OTAs), adjust corner frequencies on the capacitively coupled current conveyors, set multiplier coefficients in vector-matrix multipliers, and a variety of other operations. The floating-gate transistors may be used as switch elements, programmable resistor elements, precision current sources, and programmable transistors. Accordingly, the floating-gate transistors within the array allow on-chip programming of the characteristics of the computational elements, while still maintaining compact CABs. The arbitrary analog waveform generator may include programmable floating-gate MOS transistors for use as analog memory cells to store samples of the waveforms.
    Type: Application
    Filed: May 16, 2006
    Publication date: November 23, 2006
    Applicant: Georgia Tech Research Corporation
    Inventors: Christopher Twigg, Paul Hasler, Jordan Gray, Ravi Chawla
  • Publication number: 20060244645
    Abstract: A digital to analog converter (DAC) is described. The DAC includes an operational amplifier and a plurality of ladder elements. Each ladder element includes an epot for providing a voltage, a capacitor, and a switch for selecting between a first voltage and a reference voltage, and for providing the first selected voltage to the first capacitor. The output of the ladder elements are coupled to the inverting input of the operational amplifier. Alternatively, the ladder elements may use tunable floating-gate resistors.
    Type: Application
    Filed: May 1, 2006
    Publication date: November 2, 2006
    Applicant: Georgia Tech Research Corporation
    Inventors: Erhan Ozalevli, Paul Hasler
  • Patent number: 7109918
    Abstract: This invention exploits the synchronization properties of coupled, nonlinear oscillators arrays to perform power combining, beam steering, and beam shaping. This architecture utilizes interactions between nonlinear active elements to generate beam patterns. A nonlinear array integrates the signal processing concurrently with the transduction of the signal. This architecture differs fundamentally from passive transducer arrays in three ways: 1) the unit cells are nonlinear, 2) the array purposely couples the unit cells together, and 3) the signal processing (beam steering and shaping) is done via dynamic interactions between unit cells. The architecture extends to both 1- and 2-dimensional arrays.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: September 19, 2006
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Brian K. Meadows, Ted H. Heath, Joseph D. Neff, Edgar A. Brown, David W. Fogliatti, Visarath In, Paul Hasler, Steve P. DeWeerth, William L. Ditto, Robert A. York
  • Publication number: 20060120163
    Abstract: Systems and methods are discussed for using a floating-gate MOSFET as a programmable reference circuit. One example of the programmable reference circuit is a programmable voltage reference source, while a second example of a programmable reference circuit is a programmable reference current source. The programmable voltage reference source and/or the reference current source may be incorporated into several types of circuits, such as comparator circuits, current-mirror circuits, and converter circuits. Comparator circuits and current-mirror circuits are often incorporated into circuits such as converter circuits. Converter circuits include analog-to-digital converters and digital-to-analog converters.
    Type: Application
    Filed: January 5, 2006
    Publication date: June 8, 2006
    Inventors: Guillermo Serrano, Paul Hasler