Abstract: Techniques and apparatus for a clock and data recovery circuit to lock to data having frequency offsets relative to a local clock reference are disclosed. One embodiment includes a multi-step frequency tracking system in which each step is used to track a sub-range of frequency deviation from local clock reference. The frequency tracking sub-range of each step is selected so that the clock and data recovery system is relatively assured of achieving lock when the frequency of the incoming data lies within or is relatively near the frequency tracking sub-range of the selected step. Embodiments may use control signals to select the sub-ranges, and hence guide the frequency tracking portion of the clock and data recovery circuit to operate in a frequency tracking range that is optimized for achieving and maintaining lock.

Abstract: The method and apparatus for resetting an Active Pixel Sensor (APS) array comprises a controller for sequentially pre-resetting groups of one or more sensors in the array and then simultaneously resetting all of the sensors. The groups may be formed from one or more adjacent or non-adjacent individual sensors, rows or columns of sensors. The apparatus may further include a detector for sensing the bias voltage present on the array substrate in order for the controller to determine the number of sensors in the groups being reset. This method and apparatus assure that current flow is kept at a fairly steady level to avoid large variations in current flow that may disrupt other functioning circuits on the substrate including latch-up.

Abstract: Techniques and apparatus for a clock and data recovery circuit to lock to data having frequency offsets relative to a local clock reference are disclosed. One embodiment includes a multi-step frequency tracking system in which each step is used to track a sub-range of frequency deviation from local clock reference. The frequency tracking sub-range of each step is selected so that the clock and data recovery system is relatively assured of achieving lock when the frequency of the incoming data lies within or is relatively near the frequency tracking sub-range of the selected step. Embodiments may use control signals to select the sub-ranges, and hence guide the frequency tracking portion of the clock and data recovery circuit to operate in a frequency tracking range that is optimized for achieving and maintaining lock.

Abstract: Many electrical sensing devices include an array of transducer elements for converting external stimuli to electrical indications. Novel technologies to realize improvements in low power consumption, low noise, and analog output path which occupies minimal die area while maintaining certain data rates are disclosed. A two stage pipeline architecture of the invention in the analog output path maintains fast pixel rates with minimal ADC (analog digital converter) arrangement. A novel power supply and the use of differential amplifiers in connection with a black signal level as a reference voltage are also described.

Abstract: The method and apparatus for resetting an Active Pixel Sensor (APS) array comprises a controller for sequentially pre-resetting groups of one or more sensors in the array and then simultaneously resetting all of the sensors. The groups may be formed from one or more adjacent or non-adjacent individual sensors, rows or columns of sensors. The apparatus may further include a detector for sensing the bias voltage present on the array substrate in order for the controller to determine the number of sensors in the groups being reset. This method and apparatus assure that current flow is kept at a fairly steady level to avoid large variations in current flow that may disrupt other functioning circuits on the substrate including latch-up.

Abstract: The method and apparatus for resetting an Active Pixel Sensor (APS) array comprises a controller for sequentially pre-resetting groups of one or more sensors in the array and then simultaneously resetting all of the sensors. The groups may be formed from one or more adjacent or non-adjacent individual sensors, rows or columns of sensors. The apparatus may further include a detector for sensing the bias voltage present on the array substrate in order for the controller to determine the number of sensors in the groups being reset. This method and apparatus assure that current flow is kept at a fairly steady level to avoid large variations in current flow that may disrupt other functioning circuits on the substrate including latch-up.

Abstract: Many electrical sensing devices include an array of transducer elements for converting external stimuli to electrical indications. Novel technologies to realize improvements in low power consumption, low noise, and analog output path which occupies minimal die area while maintaining certain data rates are disclosed. A two stage pipeline architecture of the invention in the analog output path maintains fast pixel rates with minimal ADC (analog digital converter) arrangement. A novel power supply and the use of differential amplifiers in connection with a black signal level as a reference voltage are also described.

Abstract: An output signal of an image sensor pixel, which substantially avoids fixed pattern noise contributed by the readout circuitry, is provided. The apparatus, which is used to provide an output signal that is a function of the difference between two sample signals VS1 and VS2, includes first and second capacitor elements that are coupled together at a common terminal. A reference voltage VREF is first applied to the capacitor elements, then a first sample signal VS1 from the image sensor pixel is applied to the first capacitor element producing a charge that is transferred to the second capacitor element. A second sample signal VS2 from the image sensor pixel is then applied to the first capacitor element producing a charge that is also transferred to the first capacitor element such that VO=VS2?VS1+VREF.

Abstract: Many electrical sensing devices include an array of transducer elements for converting external stimuli to electrical indications. Novel technologies to realize improvements in low power consumption, low noise, and analog output path which occupies minimal die area while maintaining certain data rates are disclosed. A two stage pipeline architecture of the invention in the analog output path maintains fast pixel rates with minimal ADC (analog digital converter) arrangement. A novel power supply and the use of differential amplifiers in connection with a black signal level as a reference voltage are also described.

Abstract: The invention is directed to a method and apparatus for processing an output signal of an image sensor pixel in a manner that will substantially avoid fixed pattern noise contributed by the readout circuitry. The method comprises applying a reference voltage VREF to first and second capacitor elements that are coupled together at a common terminal, applying a first sample signal VS1 from the image sensor pixel to the first capacitor element placing a charge on it, transferring the charge from the first capacitor element to the second capacitor element, applying a second sample signal VS2 from the image sensor pixel to the first capacitor element placing a charge on it, and transferring the charge from the second capacitor element to the first capacitor element so as to provide an output signal that is a function of the difference between the second sample signal VS2 and the first sample signal VS1. In particular VO=VS2−VS1+VREF.