Patents by Inventor Paul Hubbert

Paul Hubbert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12056253
    Abstract: An interconnect including an input couplable to a source, and an encoder coupled to the input. The encoder is configured to: group information that is received from the source via a same channel; size the grouped information to a common width; and apply protection to the sized grouped information.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: August 6, 2024
    Assignee: Infineon Technologies AG
    Inventors: Ketan Dewan, Trevor Bird, Simon Cottam, Glenn Ashley Farrall, Darren Galpin, Frank Hellwig, Paul Hubbert, Dietmar Koenig, Shubhendu Mahajan, Sandeep Vangipuram
  • Publication number: 20220391524
    Abstract: An interconnect including an input couplable to a source, and an encoder coupled to the input. The encoder is configured to: group information that is received from the source via a same channel; size the grouped information to a common width; and apply protection to the sized grouped information.
    Type: Application
    Filed: June 7, 2021
    Publication date: December 8, 2022
    Inventors: Ketan Dewan, Trevor Bird, Simon Cottam, Glenn Ashley Farrall, Darren Galpin, Frank Hellwig, Paul Hubbert, Dietmar Koenig, Shubhendu Mahajan, Sandeep Vangipuram
  • Patent number: 8560899
    Abstract: The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: October 15, 2013
    Assignee: Infineon Technologies AG
    Inventors: Simon Brewerton, Neil Hastie, Paul Hubbert, Klaus Oberlaender, Robert Wiesner, Antonio Vilela, Alfred Eder, Glenn Ashley Farrall
  • Publication number: 20120030531
    Abstract: The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.
    Type: Application
    Filed: July 30, 2010
    Publication date: February 2, 2012
    Applicant: Infineon Technologies AG
    Inventors: Simon Brewerton, Neil Hastie, Paul Hubbert, Klaus Oberlaender, Robert Wiesner, Antonio Vilela, Alfred Eder