Patents by Inventor Paul Hui

Paul Hui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8188543
    Abstract: An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: May 29, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Todd C. Roggenbauer, Vishnu K. Khemka, Ronghua Zhu, Amitava Bose, Paul Hui, Xiaoqiu Huang
  • Patent number: 7820519
    Abstract: A process of forming an electronic device can include providing a semiconductor-on-insulator substrate including a substrate, a first semiconductor layer, and a buried insulating layer lying between the first semiconductor layer and the substrate. The process can also include forming a field isolation region within the semiconductor layer, and forming an opening extending through the semiconductor layer and the buried insulating layer to expose the substrate. The process can further include forming a conductive structure within the opening, wherein the conductive structure abuts the substrate.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: October 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Todd C. Roggenbauer, Vishnu K. Khemka, Ronghua Zhu, Amitava Bose, Paul Hui, Xiaoqiu Huang, Van Wong
  • Publication number: 20100196629
    Abstract: A vehicle molding includes a first elongated component formed of a first material and a second elongated component formed of a second material. The first material has a first coefficient of linear thermal expansion and the second material has a second coefficient of linear thermal expansion. The second elongated component defines a plurality of holes. A difference between the first coefficient of linear thermal expansion and the second coefficient of linear thermal expansion is at least 20×10?6 cm/cm ° C. The first material substantially fills the plurality of holes so that the second elongated component is embedded in and interlocked with the first elongated component.
    Type: Application
    Filed: January 30, 2009
    Publication date: August 5, 2010
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS, INC.
    Inventors: Julien P. Mourou, Thomas J. Pickett, Paul Hui
  • Publication number: 20080124889
    Abstract: A process of forming an electronic device can include providing a semiconductor-on-insulator substrate including a substrate, a first semiconductor layer, and a buried insulating layer lying between the first semiconductor layer and the substrate. The process can also include forming a field isolation region within the semiconductor layer, and forming an opening extending through the semiconductor layer and the buried insulating layer to expose the substrate. The process can further include forming a conductive structure within the opening, wherein the conductive structure abuts the substrate.
    Type: Application
    Filed: November 3, 2006
    Publication date: May 29, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Todd C. ROGGENBAUER, Vishnu K. KHEMKA, Ronghua ZHU, Amitava BOSE, Paul HUI, Xiaoqiu HUANG, Van WONG
  • Publication number: 20080122025
    Abstract: An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.
    Type: Application
    Filed: November 3, 2006
    Publication date: May 29, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Todd C. Roggenbauer, Vishnu K. Khemka, Ronghua Zhu, Amitava Bose, Paul Hui, Xiaoqiu Huang
  • Patent number: 7045189
    Abstract: A molding for closing a recess between a pair of body panels includes a head portion, a stem portion, and at least one leg member. The head portion has a width sufficient to close the opening when the molding is installed in the recess. The stem portion can be formed of a harder plastic material than the leg member and has a width enabling the stem portion to pass through an opening in the recess. The leg member is formed of a softer material and extends from the stem portion for frictional engagement with the side wall of the recess. A living hinge can be formed in the leg member to facilitate deflection of the leg member during insertion.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: May 16, 2006
    Assignee: General Motors of Canada Limited
    Inventors: Paul Hui, William J. Raymor
  • Publication number: 20050212318
    Abstract: A sealer tape and clip assembly in accordance with the present invention is adapted to be disposed in a recess, defined by at least one interior surface. The assembly includes a sealer tape member having an upper surface, a lower surface, and opposed side surfaces. An aperture extends through the upper surface and the lower surface, and is disposed between but does not extend through the opposed side surfaces. A clip body includes an upper portion, a lower portion, and an intermediate portion extending therebetween. The intermediate portion of the clip body is disposed in the aperture, the upper portion of the clip body engages the upper surface of the sealer tape member, and the lower portion of the clip body engages the lower surface of the sealer tape member. The sealer tape member sealingly bonds with the interior surface of the recess to secure the assembly in the recess.
    Type: Application
    Filed: March 24, 2004
    Publication date: September 29, 2005
    Inventors: Paul Hui, George Floarea
  • Patent number: 6945592
    Abstract: A sealer tape and clip assembly in accordance with the present invention is adapted to be disposed in a recess, defined by at least one interior surface. The assembly includes a sealer tape member having an upper surface, a lower surface, and opposed side surfaces. An aperture extends through the upper surface and the lower surface, and is disposed between but does not extend through the opposed side surfaces. A clip body includes an upper portion, a lower portion, and an intermediate portion extending therebetween. The intermediate portion of the clip body is disposed in the aperture, the upper portion of the clip body engages the upper surface of the sealer tape member, and the lower portion of the clip body engages the lower surface of the sealer tape member. The sealer tape member sealingly bonds with the interior surface of the recess to secure the assembly in the recess.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: September 20, 2005
    Assignee: General Motors of Canada, Ltd.
    Inventors: Paul Hui, George C. Floarea
  • Patent number: 6930027
    Abstract: A method of manufacturing a semiconductor component includes forming a first electrically insulating layer (120) and a second electrically insulating layer (130) over a semiconductor substrate (110). The method further includes etching a first trench (140) and a second trench (150) through the first and second electrically insulating layers and into the semiconductor substrate, and etching a third trench (610) through a bottom surface of the second trench and into the semiconductor substrate. The third trench has a first portion (920) and a second portion (930) interior to the first portion. The method still further includes forming a third electrically insulating layer (910) filling the first trench and the first portion of the third trench without filling the second portion of the third trench, and also includes forming a plug layer (1010) in the second portion of the third trench.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: August 16, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Vijay Parthasarathy, Vishnu Khemka, Ronghua Zhu, Amitava Bose, Todd Roggenbauer, Paul Hui, Michael C. Butner
  • Publication number: 20050042418
    Abstract: A molding for closing a recess between a pair of body panels includes a head portion, a stem portion, and at least one leg member. The head portion has a width sufficient to close the opening when the molding is installed in the recess. The stem portion can be formed of a harder plastic material than the leg member and has a width enabling the stem portion to pass through an opening in the recess. The leg member is formed of a softer material and extends from the stem portion for frictional engagement with the side wall of the recess. A living hinge can be formed in the leg member to facilitate deflection of the leg member during insertion.
    Type: Application
    Filed: August 22, 2003
    Publication date: February 24, 2005
    Inventors: Paul Hui, William Raymor
  • Publication number: 20040161931
    Abstract: A method of manufacturing a semiconductor component includes forming a first electrically insulating layer (120) and a second electrically insulating layer (130) over a semiconductor substrate (110). The method further includes etching a first trench (140) and a second trench (150) through the first and second electrically insulating layers and into the semiconductor substrate, and etching a third trench (610) through a bottom surface of the second trench and into the semiconductor substrate. The third trench has a first portion (920) and a second portion (930) interior to the first portion. The method still further includes forming a third electrically insulating layer (910) filling the first trench and the first portion of the third trench without filling the second portion of the third trench, and also includes forming a plug layer (1010) in the second portion of the third trench.
    Type: Application
    Filed: February 18, 2003
    Publication date: August 19, 2004
    Applicant: Motorola, Inc.
    Inventors: Vijay Parthasarathy, Vishnu Khemka, Ronghua Zhu, Amitava Bose, Todd Roggenbauer, Paul Hui, Michael C. Butner
  • Patent number: 6734524
    Abstract: An electronic component includes a semiconductor substrate (110), an epitaxial semiconductor layer (120, 221, 222) over the semiconductor substrate, and a semiconductor region (130, 230) in the epitaxial semiconductor layer. The epitaxial semiconductor layer has an upper surface (123). A first portion (121) of the epitaxial semiconductor layer is located below the semiconductor region, and a second portion (122) of the epitaxial semiconductor layer is located above the semiconductor region. The semiconductor substrate and the first portion of the epitaxial semiconductor layer have a first conductivity type, and the semiconductor region has a second conductivity type. At least one electrically insulating trench (140, 240) extends from the upper surface of the epitaxial semiconductor layer into at least a portion of the semiconductor region. The semiconductor substrate has a doping concentration higher than a doping concentration of the first portion of the epitaxial semiconductor layer.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: May 11, 2004
    Assignee: Motorola, Inc.
    Inventors: Vijay Parthasarathy, Vishnu Khemka, Ronghua Zhu, Amitava Bose, Todd Roggenbauer, Paul Hui