Abstract: A method of forming a compact model for an electrical device includes obtaining shape information for the device and obtaining nominal information for the device. The method also includes merging the shape information and the nominal information to form composite data, and fitting the compact model to the composite data.

Abstract: A structure, apparatus and method for deterring the temperature of an active region in semiconductor, particularly a FET is provided. A pair FETs are arranged on a silicon island a prescribed distance from one another where the silicon island is surrounded by a thermal insulator. One FET is heated by a current driven therethrough. The other FET functions as a temperature sensor by having a change in an electrical characteristic versus temperature monitored. By arranging multiple pairs of FETs separated by different known distances, the temperature of the active region of one of the FETs may be determined during operation at various driving currents.

Abstract: A system and method for developing condensed netlists for sub-circuits within an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists rather than full netlists. An IC layout is segmented into a plurality of sub-circuits, each comprising a group of one or more of a given type of active devices connected to (i.e., sharing) the same electrical sub-circuit terminals through a similar resistive network (i.e. such that they are subjected to approximately the same overall combined parasitic resistances). Full netlists corresponding to the sub-circuits are extracted from the layout and condensed. Each condensed netlist accounts for performance variations (e.g., as a function of variations in operating power supply voltages, operating temperatures and, optionally, self-heating and/or stress) exhibited by the active devices and resistive network in a sub-circuit.

Abstract: A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance.

Abstract: A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value.

Abstract: A method of forming a compact model for an electrical device includes obtaining shape information for the device and obtaining nominal information for the device. The method also includes merging the shape information and the nominal information to form composite data, and fitting the compact model to the composite data.

Abstract: A system and method for developing condensed netlists for sub-circuits within an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists rather than full netlists. An IC layout is segmented into a plurality of sub-circuits, each comprising a group of one or more of a given type of active devices connected to (i.e., sharing) the same electrical sub-circuit terminals through a similar resistive network (i.e. such that they are subjected to approximately the same overall combined parasitic resistances). Full netlists corresponding to the sub-circuits are extracted from the layout and condensed. Each condensed netlist accounts for performance variations (e.g., as a function of variations in operating power supply voltages, operating temperatures and, optionally, self-heating and/or stress) exhibited by the active devices and resistive network in a sub-circuit.

Abstract: A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance.

Abstract: A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance.

Abstract: A structure, apparatus and method for deterring the temperature of an active region in semiconductor, particularly a FET is provided. A pair FETs are arranged on a silicon island a prescribed distance from one another where the silicon island is surrounded by a thermal insulator. One FET is heated by a current driven therethrough. The other FET functions as a temperature sensor by having a change in an electrical characteristic versus temperature monitored. By arranging multiple pairs of FETs separated by different known distances, the temperature of the active region of one of the FETs may be determined during operation at various driving currents.

Abstract: A structure, apparatus and method for deterring the temperature of an active region in semiconductor, particularly a FET is provided. A pair FETs are arranged on a silicon island a prescribed distance from one another where the silicon island is surrounded by a thermal insulator. One FET is heated by a current driven therethrough. The other FET functions as a temperature sensor by having a change in an electrical characteristic versus temperature monitored. By arranging multiple pairs of FETs separated by different known distances, the temperature of the active region of one of the FETs may be determined during operation at various driving currents.

Abstract: A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value.

Abstract: A method comprises determining a poly-gate temperature for a given device and determining channel temperatures of monitor devices. The method further includes extrapolating channel temperatures of the monitor devices to obtain a channel temperature for the given device. The difference in temperature (?T value) is determined for the given device based on the poly-gate temperature and the channel temperature.

Abstract: A system and method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, the transistor including an active device (RX) area over which the gate is formed and over which the conductive line feature extends. The method includes providing an analytical model representation including a function for modeling a lithographic flare effect impacting the active device area width; and, from the modeling function, relating an effective change in active device area width (deltaW adder) as a function of a distance from a defined edge of the RX area. Then, transistor model parameter values in a transistor compact model for the device are updated to include deltaW adder values to be added to a built-in deltaW value.

Abstract: A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive landing pad feature disposed near an edge of the active device area in a circuit to be modeled. The method includes determining a distance between an edge defined by the landing pad feature to an edge of the active device area, and, from modeling a lithographic rounding effect of the landing pad feature, determining changes in width of the active device area as a function of the distance between an edge defined by the landing pad feature to an edge of the active device area. From these data, an effective change in active device area width (deltaW adder) is related to the determined distance.

Abstract: A structure, apparatus and method for deterring the temperature of an active region in semiconductor, particularly a FET is provided. A pair FETs are arranged on a silicon island a prescribed distance from one another where the silicon island is surrounded by a thermal insulator. One FET is heated by a current driven therethrough. The other FET functions as a temperature sensor by having a change in an electrical characteristic versus temperature monitored. By arranging multiple pairs of FETs separated by different known distances, the temperature of the active region of one of the FETs may be determined during operation at various driving currents.

Abstract: A method comprises determining a poly-gate temperature for a given device and determining channel temperatures of monitor devices. The method further includes extrapolating channel temperatures of the monitor devices to obtain a channel temperature for the given device. The difference in temperature (?T value) is determined for the given device based on the poly-gate temperature and the channel temperature.

Abstract: A structure, apparatus and method for deterring the temperature of an active region in semiconductor, particularly a FET is provided. A pair FETs are arranged on a silicon island a prescribed distance from one another where the silicon island is surrounded by a thermal insulator. One FET is heated by a current driven therethrough. The other FET functions as a temperature sensor by having a change in an electrical characteristic versus temperature monitored. By arranging multiple pairs of FETs separated by different known distances, the temperature of the active region of one of the FETs may be determined during operation at various driving currents.

Abstract: A ladder-type gate structure for a silicon-on-insulator (SOI) four-terminal semiconductor device is disclosed. The structure includes a gate having a first and second portion, a body region, which is under the first portion of the gate, a body contact, which is adjacent to the second portion of the gate, and a plurality of body contacts connecting the body region to the body contact through a drain region. The gate structure provides an independently controlled body region and includes a substantially uniform voltage across the body region in the SOI semiconductor device.

Abstract: A structure, apparatus and method for deterring the temperature of an active region in semiconductor, particularly a FET is provided. A pair FETs are arranged on a silicon island a prescribed distance from one another where the silicon island is surrounded by a thermal insulator. One FET is heated by a current driven therethrough. The other FET functions as a temperature sensor by having a change in an electrical characteristic versus temperature monitored. By arranging multiple pairs of FETs separated by different known distances, the temperature of the active region of one of the FETs may be determined during operation at various driving currents.