Abstract: Systems and methods are disclosed for spur mitigation for pulse signal drivers in radio frequency (RF) devices. An RF integrated circuit includes RF circuitry and analog-to-digital (ADC) circuitry. The RF circuitry operates using a local oscillator (LO) clock to receive and/or transmit RF signals, and the ADC circuitry samples one or more analog input signals and has internal timing based upon a raw digital clock. A retime circuit receives the raw digital clock and the LO clock and has a retimed clock as an output. The retimed clock represents the raw digital clock retimed with the LO clock. While other digital circuitry is timed using the raw digital clock, one or more drivers are timed by the retimed clock and provide pulse output signals to output pads. Having the drivers timed with the retimed clock and other digital circuitry timed with the raw digital clock improves overall performance.

Abstract: Systems and methods are disclosed for spur mitigation for pulse signal drivers in radio frequency (RF) devices. An RF integrated circuit includes RF circuitry and analog-to-digital (ADC) circuitry. The RF circuitry operates using a local oscillator (LO) clock to receive and/or transmit RF signals, and the ADC circuitry samples one or more analog input signals and has internal timing based upon a raw digital clock. A retime circuit receives the raw digital clock and the LO clock and has a retimed clock as an output. The retimed clock represents the raw digital clock retimed with the LO clock. While other digital circuitry is timed using the raw digital clock, one or more drivers are timed by the retimed clock and provide pulse output signals to output pads. Having the drivers timed with the retimed clock and other digital circuitry timed with the raw digital clock improves overall performance.

Abstract: An apparatus includes a memory, and a control circuit. The memory stores a vector that identifies a signal that is to be provided by an input/output (I/O) interface to a peripheral and indicates a time value. The control circuit is adapted to process the vector and route the identified signal to the peripheral and regulate a time that the signal is routed to the peripheral based on the time value.

Abstract: A technique includes receiving a request from a processor to retrieve a first instruction from a memory for a staged execution pipeline. The technique includes selectively retrieving the first instruction from the memory in response to the request based on a determination of whether the processor will execute the first instruction.

Abstract: A method includes processing descriptors to control a direct memory access (DMA) channel. The method includes synchronizing at least part of the processing, which includes processing a first descriptor of the descriptors to cause the execution to selectively pause based on a trigger value.

Abstract: An apparatus includes an integrated circuit that includes a processing core and a direct memory access (DMA) engine. The DMA engine is adapted to process descriptors to control DMA communications. The descriptors contain data indicating communication endpoints that are associated with the DMA communications. The DMA engine is adapted to use other data contained in at least one of the descriptors to control branching of descriptor execution among multiple execution paths.

Abstract: A method includes generating one of a first clock signal and a second clock signal from the other clock signal. The first clock signal is configured to be used to synchronize an operation of an analog system, and the second clock signal is configured to be used to synchronize an operation of a digital system. The method includes using a phase detector of the analog system to measure a timing of the first clock signal relative to the second clock signal; and the method includes controlling a delay element of the digital system to regulate the timing based on the measurement by the phase detector to suppress noise in the analog system.

Abstract: An apparatus includes an input/output (I/O) interface circuit that includes a memory and a controller. The memory stores a plurality of commands to regulate an input/output (I/O) interface. The commands indicate at least one I/O state of at least one I/O terminal of the I/O interface circuit and a time duration that is associated with the I/O state. The controller executes the commands to place the I/O interface in the the I/O state(s) in a predetermined sequence.

Abstract: A method includes processing descriptors to control a direct memory access (DMA) channel. The method includes synchronizing at least part of the processing, which includes processing a first descriptor of the descriptors to cause the execution to selectively pause based on a trigger value.

Abstract: An apparatus includes a memory, and a control circuit. The memory stores a vector that identifies a signal that is to be provided by an input/output (I/O) interface to a peripheral and indicates a time value. The control circuit is adapted to process the vector and route the identified signal to the peripheral and regulate a time that the signal is routed to the peripheral based on the time value.

Abstract: An apparatus includes a memory, a processor and a controller. The processor is adapted to begin executing instructions based on content stored starting at a predetermined address in the memory upon reset of the processor. The controller is adapted to, in response to the reset of the processor, provide to the processor content for the predetermined address other than the content that is stored starting at the predetermined address.

Abstract: A method includes generating one of a first clock signal and a second clock signal from the other clock signal. The first clock signal is configured to be used to synchronize an operation of an analog system, and the second clock signal is configured to be used to synchronize an operation of a digital system. The method includes using a phase detector of the analog system to measure a timing of the first clock signal relative to the second clock signal; and the method includes controlling a delay element of the digital system to regulate the timing based on the measurement by the phase detector to suppress noise in the analog system.

Abstract: An apparatus includes an integrated circuit, which includes an input terminal, a second terminal to communicate with circuitry external to the integrated circuit, a multiplexer, a level shifter and a processor. The multiplexer is adapted to selectively couple the input terminal, the level shifter and the second output terminal together.

Abstract: An apparatus includes an integrated circuit, which includes an input terminal, a second terminal to communicate with circuitry external to the integrated circuit, a multiplexer, a level shifter and a processor. The multiplexer is adapted to selectively couple the input terminal, the level shifter and the second output terminal together.

Abstract: A technique includes receiving a request from a processor to retrieve a first instruction from a memory for a staged execution pipeline. The technique includes selectively retrieving the first instruction from the memory in response to the request based on a determination of whether the processor will execute the first instruction.

Abstract: An apparatus includes a memory, a processor and a controller. The processor is adapted to begin executing instructions based on content stored starting at a predetermined address in the memory upon reset of the processor. The controller is adapted to, in response to the reset of the processor, provide to the processor content for the predetermined address other than the content that is stored starting at the predetermined address.