Patents by Inventor Paul J. Clapis

Paul J. Clapis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5610102
    Abstract: A method for co-registering a semiconductor wafer (14) undergoing work in one or more blind process modules (10), (12) requires a means (16), (18) for consistently and repeatably registering the semiconductor wafer (14) to each process module (10), (12). Given this consistent and repeatable singular wafer registration means (16), (18), the location of the coordinate axes of each process module (10), (12) is determined with respect to the position of the semiconductor wafer (14) that is registered therein.
    Type: Grant
    Filed: November 15, 1993
    Date of Patent: March 11, 1997
    Assignee: Integrated Process Equipment Corp.
    Inventors: George J. Gardopee, Paul J. Clapis, Joseph P. Prusak, Sherman K. Poultney
  • Patent number: 5555472
    Abstract: The thicknesses of a first layer and of a second layer on a semiconductor wafer can be measured together by assuming that the second layer has a substantially uniform thickness. The thicknesses are measured by measuring reflectivity as a function of wavelength at a plurality of points on the wafer to provide a plurality of signatures, comparing each signature with signatures from libraries of theoretical signatures by calculating an error value associated with each signature; and determining the minimum error value. Each library is based upon a unique assumed thickness of the second layer. Thus, the thickness of the second layer is determined by identifying the library associated with the minimum error value.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: September 10, 1996
    Assignee: Integrated Process Equipment Corp.
    Inventors: Paul J. Clapis, Keith E. Daniell