Patents by Inventor Paul J. Diglio

Paul J. Diglio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230185037
    Abstract: An electronic device comprises an electro-optical circuit package including at least photonic integrated circuit (PIC) having at least one light source and a package substrate; a printed circuit (PCB) including at least one optical connector to receive light from the at least one light source; and multiple liquid metal electrical contacts disposed between the package substrate and the PCB.
    Type: Application
    Filed: December 10, 2021
    Publication date: June 15, 2023
    Inventors: Eric J. M. Moret, Pooya Tadayon, Karumbu Meyyappan, Paul J. Diglio
  • Patent number: 11674980
    Abstract: Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: June 13, 2023
    Assignee: Intel Corporation
    Inventors: Paul J. Diglio, Joseph F. Walczyk
  • Publication number: 20230095039
    Abstract: Technologies for optical coupling to photonic integrated circuit (PIC) dies are disclosed. In the illustrative embodiment, a lens assembly with one or more lenses is positioned to collimate light coming out of one or more waveguides in the PIC die. Part of the illustrative lens assembly extends above a top surface of the PIC die and is in contact with the PIC die. The top surface of the PIC die establishes the vertical positioning of the lens assembly. In the illustrative embodiment, the lens assembly is positioned at least partially inside a cavity defined within the PIC die, which allows the lens assembly to be integrated at the wafer level, before singulation into individual dies.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 30, 2023
    Applicant: Intel Corporation
    Inventors: Srikant Nekkanty, Pooya Tadayon, Xavier F. Brun, Wesley B. Morgan, John M. Heck, Joseph F. Walczyk, Paul J. Diglio
  • Patent number: 11543454
    Abstract: Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Paul J. Diglio, Pooya Tadayon, Karumbu Meyyappan
  • Publication number: 20200371136
    Abstract: Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Applicant: Intel Corporation
    Inventors: Paul J. Diglio, Joseph F. Walczyk
  • Patent number: 10775414
    Abstract: Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Paul J. Diglio, Joseph F. Walczyk
  • Publication number: 20200096567
    Abstract: Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Applicant: Intel Corporation
    Inventors: Paul J. Diglio, Pooya Tadayon, Karumbu Meyyappan
  • Patent number: 10499461
    Abstract: A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Mohit Mamodia, Kyle Yazzie, Dingying Xu, Kuang Liu, Paul J. Diglio, Pramod Malatkar
  • Patent number: 10393592
    Abstract: Disclosed is a system for measuring a surface temperature. The system may comprise a printed circuit board, an insulator block, a conductive probe, a plurality of temperature sensors, and a plurality of compressive contact pins. The conductive probe may have a first surface and a second surface opposite the first surface. The conductive probe may be coupled to the insulator block. The plurality of temperature sensors may be coupled to the insulator block and translatable in a first direction within the insulator block. Translation of the plurality of temperature sensors in the first direction may cause each of the plurality of temperature sensors to contact the first surface of the conductive probe. The plurality of compressive contact pins may each be electrically couple a corresponding temperature sensor to the printed circuit board.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventor: Paul J. Diglio
  • Publication number: 20190101570
    Abstract: Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: Intel Corporation
    Inventors: PAUL J. DIGLIO, JOSEPH F. WALCZYK
  • Patent number: 10030916
    Abstract: A heat transfer apparatus is described having a manifold. The manifold has a surface having a fluidic exit opening and a fluidic entrance opening. A fluid is to flow from the fluidic exit opening and into the fluidic entrance opening. The manifold has a protrusion emanating from the surface between the fluidic exit opening and the fluidic entrance opening. An apparatus is described having a thermally conductive grooved structure. The thermally conductive grooved structure has a surface having first and second cavities to form first and second fluidic channels. The thermally conductive grooved structure has a protrusion emanating from between the cavities. The protrusion has side surfaces to form parts of the first and second fluidic channels.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Phi Hung Thanh, Paul J. Diglio, John C. Johnson, Jarett L. Rinaldi, Arnab Choudhury
  • Publication number: 20180172521
    Abstract: Disclosed is a system for measuring a surface temperature. The system may comprise a printed circuit board, an insulator block, a conductive probe, a plurality of temperature sensors, and a plurality of compressive contact pins. The conductive probe may have a first surface and a second surface opposite the first surface. The conductive probe may be coupled to the insulator block. The plurality of temperature sensors may be coupled to the insulator block and translatable in a first direction within the insulator block. Translation of the plurality of temperature sensors in the first direction may cause each of the plurality of temperature sensors to contact the first surface of the conductive probe. The plurality of compressive contact pins may each be electrically couple a corresponding temperature sensor to the printed circuit board.
    Type: Application
    Filed: December 21, 2016
    Publication date: June 21, 2018
    Inventor: Paul J. Diglio
  • Publication number: 20170176516
    Abstract: A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Mohit Mamodia, Kyle Yazzie, Dingying David Xu, Kuang Liu, Paul J. Diglio, Pramod Malatkar
  • Patent number: 9638747
    Abstract: Placing integrated circuit devices using a perturbation is described. In one example, a testing platform has a circuit board. A socket is on the board for receiving and connecting to an integrated circuit package. The socket has an array of pins to engage connection bumps on a surface of the package and a biasing feature to guide the package into alignment with the pins of the socket. A perturbation source induces movement of the package into alignment with the pins of the socket.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Paul J. Diglio, Nader N. Abazarnia, Christopher R. Schroeder, Rene J. Sanchez, Morten S. Jensen
  • Publication number: 20160377658
    Abstract: Improved fluid flow is described for a temperature control actuator that is used in semiconductor device test. In one example, the apparatus includes a top plate configured to thermally connect to a semiconductor device under test, a channel plate thermally connected to the top plate and having a plurality of fluid channels to receive a thermally controlled fluid from an inlet to exchange heat with the thermally controlled fluid in the channel and to eliminate the thermally controlled fluid to an outlet, a manifold to provide the thermally controlled fluid to the inlet and to receive the thermally controlled fluid through the outlet, and a flow guide in the channel thermally connected to the top plate.
    Type: Application
    Filed: June 24, 2015
    Publication date: December 29, 2016
    Applicant: INTEL CORPORATION
    Inventors: Paul J. DIGLIO, John C. JOHNSON, Weihua TANG
  • Publication number: 20160033208
    Abstract: A heat transfer apparatus is described having a manifold. The manifold has a surface having a fluidic exit opening and a fluidic entrance opening. A fluid is to flow from the fluidic exit opening and into the fluidic entrance opening. The manifold has a protrusion emanating from the surface between the fluidic exit opening and the fluidic entrance opening. An apparatus is described having a thermally conductive grooved structure. The thermally conductive grooved structure has a surface having first and second cavities to form first and second fluidic channels. The thermally conductive grooved structure has a protrusion emanating from between the cavities. The protrusion has side surfaces to form parts of the first and second fluidic channels.
    Type: Application
    Filed: July 29, 2014
    Publication date: February 4, 2016
    Inventors: PHI HUNG THANH, PAUL J. DIGLIO, JOHN C. JOHNSON, JARETT L. RINALDI, ARNAB CHOUDHURY
  • Publication number: 20150185281
    Abstract: Placing integrated circuit devices using a perturbation is described. In one example, a testing platform has a circuit board. A socket is on the board for receiving and connecting to an integrated circuit package. The socket has an array of pins to engage connection bumps on a surface of the package and a biasing feature to guide the package into alignment with the pins of the socket. A perturbation source induces movement of the package into alignment with the pins of the socket.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Inventors: Paul J. Diglio, Nader N. Abazarnia, Christopher R. Schroeder, Rene J. Sanchez, Morten S. Jensen