Patents by Inventor Paul J. Diglio
Paul J. Diglio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230185037Abstract: An electronic device comprises an electro-optical circuit package including at least photonic integrated circuit (PIC) having at least one light source and a package substrate; a printed circuit (PCB) including at least one optical connector to receive light from the at least one light source; and multiple liquid metal electrical contacts disposed between the package substrate and the PCB.Type: ApplicationFiled: December 10, 2021Publication date: June 15, 2023Inventors: Eric J. M. Moret, Pooya Tadayon, Karumbu Meyyappan, Paul J. Diglio
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Patent number: 11674980Abstract: Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.Type: GrantFiled: August 13, 2020Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Paul J. Diglio, Joseph F. Walczyk
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Publication number: 20230095039Abstract: Technologies for optical coupling to photonic integrated circuit (PIC) dies are disclosed. In the illustrative embodiment, a lens assembly with one or more lenses is positioned to collimate light coming out of one or more waveguides in the PIC die. Part of the illustrative lens assembly extends above a top surface of the PIC die and is in contact with the PIC die. The top surface of the PIC die establishes the vertical positioning of the lens assembly. In the illustrative embodiment, the lens assembly is positioned at least partially inside a cavity defined within the PIC die, which allows the lens assembly to be integrated at the wafer level, before singulation into individual dies.Type: ApplicationFiled: September 17, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Srikant Nekkanty, Pooya Tadayon, Xavier F. Brun, Wesley B. Morgan, John M. Heck, Joseph F. Walczyk, Paul J. Diglio
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Patent number: 11543454Abstract: Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.Type: GrantFiled: September 25, 2018Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Paul J. Diglio, Pooya Tadayon, Karumbu Meyyappan
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Publication number: 20200371136Abstract: Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.Type: ApplicationFiled: August 13, 2020Publication date: November 26, 2020Applicant: Intel CorporationInventors: Paul J. Diglio, Joseph F. Walczyk
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Patent number: 10775414Abstract: Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.Type: GrantFiled: September 29, 2017Date of Patent: September 15, 2020Assignee: Intel CorporationInventors: Paul J. Diglio, Joseph F. Walczyk
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Publication number: 20200096567Abstract: Embodiments herein relate to a test probe. The test probe may have a first plurality of beams and a second plurality of beams. An intermediate substrate may be positioned between the first plurality of beams and the second plurality of beams. In embodiments, both the first and second plurality of beams may be angled. Other embodiments may be described or claimed.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Applicant: Intel CorporationInventors: Paul J. Diglio, Pooya Tadayon, Karumbu Meyyappan
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Patent number: 10499461Abstract: A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.Type: GrantFiled: December 21, 2015Date of Patent: December 3, 2019Assignee: Intel CorporationInventors: Mohit Mamodia, Kyle Yazzie, Dingying Xu, Kuang Liu, Paul J. Diglio, Pramod Malatkar
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Patent number: 10393592Abstract: Disclosed is a system for measuring a surface temperature. The system may comprise a printed circuit board, an insulator block, a conductive probe, a plurality of temperature sensors, and a plurality of compressive contact pins. The conductive probe may have a first surface and a second surface opposite the first surface. The conductive probe may be coupled to the insulator block. The plurality of temperature sensors may be coupled to the insulator block and translatable in a first direction within the insulator block. Translation of the plurality of temperature sensors in the first direction may cause each of the plurality of temperature sensors to contact the first surface of the conductive probe. The plurality of compressive contact pins may each be electrically couple a corresponding temperature sensor to the printed circuit board.Type: GrantFiled: December 21, 2016Date of Patent: August 27, 2019Assignee: Intel CorporationInventor: Paul J. Diglio
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Publication number: 20190101570Abstract: Planar error between a probe card and a semiconductor wafer may be reduced with a low-profile gimbal platform. The low-profile gimbal platform may be coupled between a probe card and a tester head. The low-profiled gimbal platform includes a number of linear actuators and pistons that are used to perform high-precision in situ planarity adjustments to the probe card to achieve co-planarity between the probe card and the semiconductor wafer. The in situ planarity adjustments may reduce the likelihood of malfunctions due to misalignment of the probe card.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: Intel CorporationInventors: PAUL J. DIGLIO, JOSEPH F. WALCZYK
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Patent number: 10030916Abstract: A heat transfer apparatus is described having a manifold. The manifold has a surface having a fluidic exit opening and a fluidic entrance opening. A fluid is to flow from the fluidic exit opening and into the fluidic entrance opening. The manifold has a protrusion emanating from the surface between the fluidic exit opening and the fluidic entrance opening. An apparatus is described having a thermally conductive grooved structure. The thermally conductive grooved structure has a surface having first and second cavities to form first and second fluidic channels. The thermally conductive grooved structure has a protrusion emanating from between the cavities. The protrusion has side surfaces to form parts of the first and second fluidic channels.Type: GrantFiled: July 29, 2014Date of Patent: July 24, 2018Assignee: Intel CorporationInventors: Phi Hung Thanh, Paul J. Diglio, John C. Johnson, Jarett L. Rinaldi, Arnab Choudhury
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Publication number: 20180172521Abstract: Disclosed is a system for measuring a surface temperature. The system may comprise a printed circuit board, an insulator block, a conductive probe, a plurality of temperature sensors, and a plurality of compressive contact pins. The conductive probe may have a first surface and a second surface opposite the first surface. The conductive probe may be coupled to the insulator block. The plurality of temperature sensors may be coupled to the insulator block and translatable in a first direction within the insulator block. Translation of the plurality of temperature sensors in the first direction may cause each of the plurality of temperature sensors to contact the first surface of the conductive probe. The plurality of compressive contact pins may each be electrically couple a corresponding temperature sensor to the printed circuit board.Type: ApplicationFiled: December 21, 2016Publication date: June 21, 2018Inventor: Paul J. Diglio
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Publication number: 20170176516Abstract: A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.Type: ApplicationFiled: December 21, 2015Publication date: June 22, 2017Applicant: INTEL CORPORATIONInventors: Mohit Mamodia, Kyle Yazzie, Dingying David Xu, Kuang Liu, Paul J. Diglio, Pramod Malatkar
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Patent number: 9638747Abstract: Placing integrated circuit devices using a perturbation is described. In one example, a testing platform has a circuit board. A socket is on the board for receiving and connecting to an integrated circuit package. The socket has an array of pins to engage connection bumps on a surface of the package and a biasing feature to guide the package into alignment with the pins of the socket. A perturbation source induces movement of the package into alignment with the pins of the socket.Type: GrantFiled: December 27, 2013Date of Patent: May 2, 2017Assignee: Intel CorporationInventors: Paul J. Diglio, Nader N. Abazarnia, Christopher R. Schroeder, Rene J. Sanchez, Morten S. Jensen
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Publication number: 20160377658Abstract: Improved fluid flow is described for a temperature control actuator that is used in semiconductor device test. In one example, the apparatus includes a top plate configured to thermally connect to a semiconductor device under test, a channel plate thermally connected to the top plate and having a plurality of fluid channels to receive a thermally controlled fluid from an inlet to exchange heat with the thermally controlled fluid in the channel and to eliminate the thermally controlled fluid to an outlet, a manifold to provide the thermally controlled fluid to the inlet and to receive the thermally controlled fluid through the outlet, and a flow guide in the channel thermally connected to the top plate.Type: ApplicationFiled: June 24, 2015Publication date: December 29, 2016Applicant: INTEL CORPORATIONInventors: Paul J. DIGLIO, John C. JOHNSON, Weihua TANG
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Publication number: 20160033208Abstract: A heat transfer apparatus is described having a manifold. The manifold has a surface having a fluidic exit opening and a fluidic entrance opening. A fluid is to flow from the fluidic exit opening and into the fluidic entrance opening. The manifold has a protrusion emanating from the surface between the fluidic exit opening and the fluidic entrance opening. An apparatus is described having a thermally conductive grooved structure. The thermally conductive grooved structure has a surface having first and second cavities to form first and second fluidic channels. The thermally conductive grooved structure has a protrusion emanating from between the cavities. The protrusion has side surfaces to form parts of the first and second fluidic channels.Type: ApplicationFiled: July 29, 2014Publication date: February 4, 2016Inventors: PHI HUNG THANH, PAUL J. DIGLIO, JOHN C. JOHNSON, JARETT L. RINALDI, ARNAB CHOUDHURY
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Publication number: 20150185281Abstract: Placing integrated circuit devices using a perturbation is described. In one example, a testing platform has a circuit board. A socket is on the board for receiving and connecting to an integrated circuit package. The socket has an array of pins to engage connection bumps on a surface of the package and a biasing feature to guide the package into alignment with the pins of the socket. A perturbation source induces movement of the package into alignment with the pins of the socket.Type: ApplicationFiled: December 27, 2013Publication date: July 2, 2015Inventors: Paul J. Diglio, Nader N. Abazarnia, Christopher R. Schroeder, Rene J. Sanchez, Morten S. Jensen