Abstract: A power tool having multiple wireless communication states and a method of wirelessly communicating by a power tool. The power tool includes a motor, a battery pack interface that selectively receives a battery pack, a backup power source, and a wireless communication controller coupled to the backup power source and the battery pack interface. The wireless communication controller operates in a connectable state when coupled to a battery pack and transmits tool operational data to the external device and receives tool configuration data from the external device. The wireless communication controller operates in an advertisement state when the wireless communication controller is coupled to and powered by the backup power source. In the advertisement state, the wireless communication controller is configured to transmit the unique tool identifier. The external device may also display an indication of the communication state of the power tool.

Abstract: A microporous biocomposite that is suitable for surgical implantation in an avascular environment is provided. The microporous biocomposite includes (1) a polymer scaffold having a thickness less than about 100 ?m and nodal structures that extend to at least one surface of the polymer scaffold and (2) a hydrophilic coating on the polymer scaffold. In some embodiments, the porous scaffold is a microporous biomaterial with nodal structures that extend from a first surface to a second surface of the microporous biomaterial. The hydrophilic coating may be a node and fibril coating. The microporous biocomposite allows for the integration and sustained viability of epithelial cells on the surface thereof as well as tissue integration and the internal colonization of the biomaterial with other cell types, such as keratocytes and fibroblasts. In at least one embodiment, the microporous biocomposite may be incorporated into an artificial corneal implant or in other avascular mesoplants.

Abstract: The present invention is an artificial cornea designed to restore vision in patients who are not candidates to receive a natural cornea transplant (allograft). The present device construction involves the use of a biocompatible, non-porous optic disk intimately bonded to one or more anchoring layers of porous polymeric material, and a unique sealing region which enhances sealing of the artificial cornea in the recipient's eye.

Abstract: An electronic chip package is provided having a laminated substrate. The laminated substrate includes at least one conductive layer and at least one dielectric layer which is bonded to the conductive layer. The dielectric layer has a glass transition temperature Tg greater than 200° C. and a volumetric coefficient of thermal expansion of ≦75 ppm/° C. A semiconductor device is electrically attached to the laminated substrate.

Abstract: An electronic chip package is provided having a laminated substrate. The laminated substrate includes at least one conductive layer and at least one dielectric layer which is bonded to the conductive layer. The dielectric layer has a glass transition temperature Tg greater than 200° C. and a volumetric coefficient of thermal expansion of ≦75 ppm/° C. A semiconductor device is electrically attached to the laminated substrate.

Abstract: A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through vias are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided then the vias do not extend through the clearances in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. This allows each substrate to perform the same. Additionally, a plurality of chip packages having the dimensionally stable core can be bonded together to obtain a high density chip package.

Abstract: A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through vias are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided then the vias do not extend through the clearances in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. This allows each substrate to perform the same. Additionally, a plurality of chip packages having the dimensionally stable core can be bonded together to obtain a high density chip package.

Abstract: A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.

Abstract: An electronic chip package is provided having a laminated substrate. The laminated substrate includes at least one conductive layer and at least one dielectric layer which is bonded to the conductive layer. The dielectric layer has a glass transition temperature T.sub.g greater than 200.degree. C. and a volumetric coefficient of thermal expansion of .ltoreq.75 ppm/.degree.C. A semiconductor device is electrically attached to the laminated substrate.

Abstract: A method of minimizing warp and die stress in the production of an electronic assembly includes connecting one surface of a die to a package, and connecting an opposite surface of the die to a lid disposed over a constraining ring that is mounted to the package. The lid has a size, shape and coefficient of thermal expansion (CTE) selected to generate a bending moment that opposes bending moments resulting from connecting the die to the package.

Abstract: The present invention generally relates to the field of integrated circuit chip packaging. More particularly, the present invention relates to methods of manufacturing integrated circuit chip packages, and methods for electrically connecting and bonding or attaching semiconductor devices to an integrated circuit chip.

Abstract: A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.

Abstract: In a method for forming redundant signal traces and corresponding electronic components, a photoresist pattern which defines a semi-additive signal image is coated on at least one first conductive layer of a composite base substrate. A barrier layer of etch-resistant metal is deposited on the first conductive layer. The photoresist is removed, thereby forming a first barrier signal trace having a first line width. Optionally, one or more vias may be formed in the substrate. A surface conductive layer is deposited on the first conductive layer, the barrier layer, and on a surface of the optional vias. A photoresist pattern is coated on the surface conductive layer which defines a subtractive signal image. Predetermined portions of the surface conductive layer and the first conductive layer are removed. The photoresist is removed forming a second signal trace in overlying relationship with the first barrier signal trace and having a second line width greater than the first line width.

Abstract: The present invention generally relates to the field of integrated circuit chip packaging. More particularly, the present invention relates to methods of manufacturing integrated circuit chip packages, and methods for electrically connecting and bonding or attaching semiconductor devices to an integrated circuit chip.

Abstract: The present invention generally relates to the field of integrated circuit chip packaging. More particularly, the present invention relates to methods of manufacturing integrated circuit chip packages, and methods for electrically connecting and bonding or attaching semiconductor devices to an integrated circuit chip.

Abstract: A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.

Abstract: A method of minimizing warp and die stress in the production of an electronic assembly includes connecting one surface of a die to a package, and connecting an opposite surface of the die to a lid disposed over a constraining ring that is mounted to the package. The lid has a size, shape and coefficient of thermal expansion (CTE) selected to generate a bending moment that opposes bending moments resulting from connecting the die to the package.

Abstract: A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through vias are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided then the vias do not extend through the clearances in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. This allows each substrate to perform the same. Additionally, a plurality of chip packages having the dimensionally stable core can be bonded together to obtain a high density chip package.

Abstract: A method is provided for forming at least one raised metallic contact on an electrical circuit for permanent bonding. Generally, this method includes the following steps: providing a composite base substrate which is defined by at least a first conductive layer, a dielectric material and a second conductive layer; removing a portion of the first conductive layer to expose the dielectric material; removing the exposed portion of the dielectric material to the second conductive layer, thereby forming a depression; depositing at least one layer of solder on at least side wall portions of the depression; depositing at least one layer of copper; removing the second conductive layer; and completely removing the dielectric material to said first conductive layer thereby forming a raised solder contact which extends perpendicularly away from the first conductive layer.