Patents by Inventor Paul J. Koep

Paul J. Koep has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240021565
    Abstract: A solder material comprising a solder alloy and a thermal conductivity modifying component. The solder material has a bulk thermal conductivity of between about 75 and about 150 W/m-K and is usable in enhancing the thermal conductivity of the solder, allowing for optimal heat transfer and reliability in electronic packaging applications.
    Type: Application
    Filed: September 19, 2023
    Publication date: January 18, 2024
    Inventors: Angelo GULINO, Bogdan BANKIEWICZ, Oscar KHASELEV, Anna LIFTON, Michael T. MARCZI, Girard SIDONE, Paul SALERNO, Paul J. KOEP
  • Patent number: 11842974
    Abstract: A solder material comprising a solder alloy and a thermal conductivity modifying component. The solder material has a bulk thermal conductivity of between about 75 and about 150 W/m-K and is usable in enhancing the thermal conductivity of the solder, allowing for optimal heat transfer and reliability in electronic packaging applications.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: December 12, 2023
    Assignee: Alpha Assembly Solutions Inc.
    Inventors: Angelo Gulino, Bogdan Bankiewicz, Oscar Khaselev, Anna Lifton, Michael T. Marczi, Girard Sidone, Paul Salerno, Paul J. Koep
  • Publication number: 20200203304
    Abstract: A solder material comprising a solder alloy and a thermal conductivity modifying component. The solder material has a bulk thermal conductivity of between about 75 and about 150 W/m-K and is usable in enhancing the thermal conductivity of the solder, allowing for optimal heat transfer and reliability in electronic packaging applications.
    Type: Application
    Filed: May 11, 2018
    Publication date: June 25, 2020
    Inventors: Angelo GULINO, Bogdan BANKIEWICZ, Oscar KHASELEV, Anna LIFTON, Michael T. MARCZI, Girard SIDONE, Paul SALERNO, Paul J. KOEP
  • Publication number: 20140328039
    Abstract: In accordance with one or more aspects, a method of reducing void formation in a solder joint may comprise applying a solder paste deposit to a substrate, placing a solder preform in the solder paste deposit, disposing a device on the solder preform and the solder paste deposit, and processing the solder paste deposit and the solder preform to form the solder joint between the device and the substrate. In some aspects, the substrate is a printed circuit board and the device is an integrated circuit package.
    Type: Application
    Filed: September 25, 2012
    Publication date: November 6, 2014
    Inventors: Paul J. Koep, Michiel A. de Monchy, Ellen S. Tormey