Abstract: A computer system is disclosed that includes: a communications bus implemented in accordance with an Inter-IC bus specification; a bus controller coupled to the communications bus; a send machine coupled between a host processor and the bus controller; and a first-in first-out (FIFO) buffer coupled to the send machine and coupled between the host processor and the bus controller.

Abstract: A machine-readable identification register is provided on each cell of a cellular computer system. The identification register is read during system startup to identify a processor type, which may include an instruction set architecture (ISA), associated with the cell. The processor type information is used to ensure that a compatible boot image is provided to processors of the cell. In another embodiment, the system management subsystem has a version selection flag. When the version selection flag is in a first state, the compatible boot image provided to processors of the cell is a current boot image; with the selection flag in a second state the compatible boot image provided to processors of the cell is an older edition of the boot image.

Abstract: Disclosed are systems and methods for providing access to bus-mastered system resources comprising disposing a bus multiplexer between a first bus and a bus access arbiter, wherein the first bus is coupled to at least one system resource for which bus access is arbitrated by the bus access arbiter, and controlling the bus multiplexer to couple a second bus to the first bus thereby providing a link between the first bus and the second bus bypassing the bus access arbiter.

Abstract: A system for providing basic system control functions upon failure of all management processors in a computer system. During normal system operation, a plurality of management processors monitor system sensors that detect system power, temperature, and cooling fan status, and make necessary adjustments. Each management processor normally provides an output signal indicating that it is operating property. A high-availability controller monitors each of these signals to verify that there is at least one operating management processor. When none of the processors indicate that they are operating properly, the high-availability controller monitors the system sensors and updates system indicators. If a problem develops, such as failure of a power supply or a potentially dangerous increase in temperature, the high-availability controller sequentially powers down the appropriate equipment to protect the system from damage.

Abstract: The system of the invention ensures pin assignments between system board connections of printed circuit boards. A plurality of software configuration files define connections of a plurality of printed circuit boards. A mapping file correlates pin assignment attributes between the software configuration files. A processing section processes the configuration files and the mapping file to generate board schematics for the plurality of printed circuit boards with common pin assignment for the connections of each of the printed circuit boards. The software configuration files may include symbol files representing parts within the plurality of printed circuit boards. The software configuration files may include geometry files representing physical attributes of the parts. Changes to the design are automatically correlated to pin assignments through the boards and layout.

Abstract: A system for removal and replacement of core I/O devices while the rest of the computer system is powered-up and operational. The system comprises a custom form-factor core I/O card that contains a plurality of I/O devices, including a processor for managing the card's I/O functions. A command is sent to an operating system, running on a system processor external to the core I/O card, that notifies the system to stop using, and de-configure, the hardware on the core I/O card. Once the OS receives this notification, an indication that the card is ready to be removed is sent to the user. The user then removes the card from its slot and inserts a replacement card into the same slot. The system software then discovers the I/O components on the core I/O card to determine what components are available, and then configures the new I/O device(s).

Abstract: Disclosed are systems and methods for providing access to bus-mastered system resources comprising disposing a bus multiplexer between a first bus and a bus access arbiter, wherein the first bus is coupled to at least one system resource for which bus access is arbitrated by the bus access arbiter, and controlling the bus multiplexer to couple a second bus to the first bus thereby providing a link between the first bus and the second bus bypassing the bus access arbiter.

Abstract: The system of the invention ensures pin assignments between system board connections of printed circuit boards. A plurality of software configuration files define connections of a plurality of printed circuit boards. A mapping file correlates pin assignment attributes between the software configuration files. A processing section processes the configuration files and the mapping file to generate board schematics for the plurality of printed circuit boards with common pin assignment for the connections of each of the printed circuit boards. The software configuration files may include symbol files representing parts within the plurality of printed circuit boards. The software configuration files may include geometry files representing physical attributes of the parts. Changes to the design are automatically correlated to pin assignments through the boards and layout.

Abstract: The system of the invention ensures pin assignments between system board connections of printed circuit boards. A plurality of software configuration files define connections of a plurality of printed circuit boards. A mapping file correlates pin assignment attributes between the software configuration files. A processing section processes the configuration files and the mapping file to generate board schematics for the plurality of printed circuit boards with common pin assignment for the connections of each of the printed circuit boards. The software configuration files may include symbol files representing parts within the plurality of printed circuit boards. The software configuration files may include geometry files representing physical attributes of the parts. Changes to the design are automatically correlated to pin assignments through the boards and layout.

Abstract: A system for providing basic system control functions upon failure of all management processors in a computer system. During normal system operation, a plurality of management processors monitor system sensors that detect system power, temperature, and cooling fan status, and make necessary adjustments. Each management processor normally provides an output signal indicating that it is operating property. A high-availability controller monitors each of these signals to verify that there is at least one operating management processor. When none of the processors indicate that they are operating properly, the high-availability controller monitors the system sensors and updates system indicators. If a problem develops, such as failure of a power supply or a potentially dangerous increase in temperature, the high-availability controller sequentially powers down the appropriate equipment to protect the system from damage.

Abstract: An electrical connector assembly has a flexible circuit with a first end portion, a second end portion, a first surface, and a second surface. A plurality of conductors extend between the first end portion and the second end portion within the circuit. A first connector assembly is attached to the circuit first end portion. The first connector assembly has a first connector electrically connected to at least one of the plurality of conductors, a first plate substantially encompassing the first connector and located adjacent the circuit first surface, and a second plate located adjacent the circuit second surface and opposite the first plate. The first plate and the second plate are mechanically coupled.

Abstract: A system for providing basic system control functions upon failure of a management processor in a computer system. During normal system operation, a management processor monitors system sensors that detect system power, temperature, and cooling fan status, and make necessary adjustments. The management processor normally provides an output signal indicating that it is operating properly. A high-availability controller monitors each of these signals to verify that there is at least one operating management processor. When none of the processors indicate that they are operating properly, the high-availability controller monitors the system sensors and updates system indicators. If a problem develops, such as failure of a power supply or a potentially dangerous increase in temperature, the high-availability controller sequentially powers down the appropriate equipment to protect the system from damage.

Abstract: A method and apparatus is described for the in-system programming of EEPROMs with configuration code for programmable logic devices such as FPGAs. The method and apparatus is suitable for use in larger systems where not all of the EEPROMs are located on the same circuit board. Multiple board-specific serial busses are provided, where each serial bus connects to EEPROMs of a particular circuit boards and to a common configuration point having selection apparatus and a header for coupling to configuration apparatus. The method includes the steps of setting the selection apparatus to designate a particular bus, erasing at least one EEPROM coupled to the serial bus, and writing programmable logic device configuration code through the serial bus to the EEPROM. Further claims include accessing the bus prior to writing any EEPROM to verify compatibility of a code file with the selected circuit board.

Abstract: A system for removal and replacement of core I/O devices while the rest of the computer system is powered-up and operational. The system comprises a custom form-factor core I/O card that contains a plurality of I/O devices, including a processor for managing the card's I/O functions. A command is sent to an operating system, running on a system processor external to the core I/O card, that notifies the system to stop using, and de-configure, the hardware on the core I/O card. Once the OS receives this notification, an indication that the card is ready to be removed is sent to the user. The user then removes the card from its slot and inserts a replacement card into the same slot. The system software then discovers the I/O components on the core I/O card to determine what components are available, and then configures the new I/O device(s).

Abstract: The system of the invention ensures pin assignments between system board connections of printed circuit boards. A plurality of software configuration files define connections of a plurality of printed circuit boards. A mapping file correlates pin assignment attributes between the software configuration files. A processing section processes the configuration files and the mapping file to generate board schematics for the plurality of printed circuit boards with common pin assignment for the connections of each of the printed circuit boards. The software configuration files may include symbol files representing parts within the plurality of printed circuit boards. The software configuration files may include geometry files representing physical attributes of the parts. Changes to the design are automatically correlated to pin assignments through the boards and layout.