Patents by Inventor Paul J. Panaccione

Paul J. Panaccione has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7251872
    Abstract: A chip package is formed which has an array of leads, wherein successive leads are staggered in all three dimensions (X, Y, and Z) relative to one another to permit a large number of leads available in a confined space while maintaining the minimum separation necessary between adjacent leads. The leads are formed by placing asymmetric top and bottom masks on a lead frame, and partially etching the top of the lead frame, while partially and over etching the bottom of the lead frame. Although the resulting leads are staggered in three dimensions, no additional processing steps are needed beyond those used to fabricate conventional packages.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: August 7, 2007
    Assignee: International Business Machines Corporation
    Inventors: Elie Awad, Paul J. Panaccione
  • Patent number: 6815806
    Abstract: A chip package having an array of leads, wherein successive leads are staggered in all three dimensions (X, Y, and Z) relative to one another. Such a staggered arrangement permits a large number of leads available in a confined space while maintaining the minimum separation necessary between adjacent leads. The leads are formed by placing asymmetric top and bottom masks on a lead frame, and partially etching the top of the lead frame, while partially and over etching the bottom of the lead frame. Although the resulting leads are staggering in three dimensions, no additional processing steps are needed beyond those used to fabricate conventional packages.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: November 9, 2004
    Assignee: International Business Machines Corp.
    Inventors: Elie Awad, Paul J. Panaccione
  • Patent number: 5289344
    Abstract: The lead-frame in an integrated circuit package, a standard package designated SOT-89, has a plurality of leads of which at least one is an extension of a die-attach pad. At least one ground wing is formed as an extension of a peripheral portion of the die-attach pad and extends upward to approximately the plane of the top of the die. The ground wing has an upstanding portion and a horizontal portion that are at an angle to each other so as to lock the distal end of the wing in the body of encapsulating resin. An integrated circuit die having at least one electrical connection which is grounded electrically via a terminal and wire bonded to the distal part of the ground wing. A contact surface near the distal end of wing is positioned approximately in the plane of the top of the die. This ground circuit can parallel and can be redundant to a ground circuit through the die via the conductive bond that attaches the bottom of the die to the die-attach pad.
    Type: Grant
    Filed: October 8, 1992
    Date of Patent: February 22, 1994
    Assignee: Allegro Microsystems Inc.
    Inventors: Jay J. Gagnon, Paul J. Panaccione