Abstract: A program verify and erase verify control circuit is disclosed for use with an EEPROM/flash memory system wherein each memory cell can be read, erased or programmed based, in part, on the voltage level of a word line coupled to the gate of each of the memory cells. Program operations are verified by placing a worst case (i.e., highest) read voltage on the word lines of programmed memory cells. Similarly, erase operations are verified by placing a worst case (i.e., lowest) read voltage on the word lines of erased memory cells. So that there worst case voltages are stable and reproducible, they are generated using a feedback control circuit consisting of a comparator driven by a bandgap voltage reference (+1.28 VDC ), various feedback transistors and a voltage divider network. The worst case program verification voltage (+6.4 VDC) and the worst case erase verification voltage (+4.

Abstract: A program drain voltage control system is disclosed for use within an EPROM/flash memory system wherein each memory cell is coupled in series with plural y selection transistors. When the EPROM/flash memory system is in programming mode, the control system maintains the program drain voltage of EPROM/flash memory cells being programmed at a target drain voltage (+6.1 VDC ). Drain voltage control is accomplished using a current control circuit and a voltage control circuit. The voltage control circuit uses a comparator driven by a voltage reference signal (+1.28 VDC) derived from the bandgap reference and by a voltage divider output. When the output from the voltage divider is larger than the reference voltage, the comparator output goes high, turning on a pulldown transistor, which pulls down the node where the target voltage is to be established.