Abstract: A power MOS transistor, including source, drain, and gate electrodes, comprises a substrate of a semiconductor material of one conductivity type having first and second opposed surfaces; a drain region extending through the substrate between the surfaces; a plurality of spaced body regions of the opposite conductivity type extending into the substrate from the first surface; and a source region of the one conductivity type extending into the substrate from the first surface within each of the body regions, the interface of each of the source regions with its respective body region at the first surface being spaced from the interface of its respective body region and the drain region at the first surface to form a channel region therebetween. A gate electrode overlies and is insulated from the first surface and extends across the channel regions. A conductive electrode extends over and is insulated from the gate electrode, and contacts at least a portion of the source regions.

Abstract: The present invention relates to a power MOS transistor having a current limiting circuit incorporated in the same substrate as the transistor. The power MOS transistor includes a drain region extending through the substrate between opposed first and second surfaces, a plurality of body regions in the substrate at the first surface, a separate source region in the substrate at the first surface within each body region and a channel extending across each body region between its junction with its respective source region and its junction with the drain region. A conductive gate is over and insulated from the first surface and extends over the channel regions. A first conductive electrode extends over and is insulated from the gate and contacts a first portion of the source regions. A second conductive electrode extends over and is insulated from the gate and contacts a second portion of the source regions. The second portion contains a smaller number of the source regions than the first portion.