Patents by Inventor Paul Jacobs

Paul Jacobs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11505879
    Abstract: Processes for making high-performance polyethylene multi-filament yarn are disclosed which include the steps of a) making a solution of ultra-high molar mass polyethylene in a solvent; b) spinning of the solution through a spinplate containing at least 5 spinholes into an air-gap to form fluid filaments, while applying a draw ratio DRfluid; c) cooling the fluid filaments to form solvent-containing gel filaments; d) removing at least partly the solvent from the filaments; and e) drawing the filaments in at least one step before, during and/or after said solvent removing, while applying a draw ratio DRsolid of at least 4, wherein in step b) each spinhole comprises a contraction zone of specific dimension and a downstream zone of diameter Dn and length Dn with Ln/Dn of from 0 to at most 25, to result in a draw ratio DRfluid=DRsp*DRag of at least 150, wherein DRsp is the draw ratio in the spinholes and DRag is the draw ratio in the air-gap, with DRsp being greater than 1 and DRag at least 1.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: November 22, 2022
    Assignee: DSM IP ASSETS B.V.
    Inventors: Joseph Arnold Paul Maria Simmelink, Jacobus Johannes Mencke, Martinus Johannes Nicolaas Jacobs, Roeloef Marissen
  • Patent number: 11501047
    Abstract: A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests (“LBIST”) trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: November 15, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sean Michael Carey, Richard Frank Rizzolo, Bodo Hoppe, Divya Kumudprakash Joshi, Paul Jacob Logsdon, Sreekala Anandavally, William Rurik
  • Publication number: 20220360428
    Abstract: Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.
    Type: Application
    Filed: July 8, 2022
    Publication date: November 10, 2022
    Inventors: Morris Jacob Creeger, Tianfang Liu, Frederick Furtek, Paul L. Master
  • Patent number: 11491458
    Abstract: A method for producing a chemical reactor device based on a fluid flow comprises obtaining a substrate with a fluid channel defined by a channel wall, in which an ordered set of silicon pillar structures is positioned in the fluid channel and electrochemically anodising at least the silicon pillar structures to make the silicon pillar structures porous at least to a certain depth. After the anodising, the substrate and pillar structures are thermally treated, the treatment being carried out at a temperature, with a duration and in an atmosphere such that any silicon oxide layer formed has a thickness of less than 20 nm. The substrate and the pillar structures are further functionalized.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: November 8, 2022
    Assignee: PHARMAFLUIDICS NV
    Inventors: Wim De Malsche, Jeff Op De Beeck, Paul Jacobs, Bo Claerebout
  • Publication number: 20220353425
    Abstract: The present disclosure generally relates to user interfaces for altering visual media. In some embodiments, user interfaces capturing visual media (e.g., via a synthetic depth-of-field effect), playing back visual media (e.g., via a synthetic depth-of-field effect), editing visual media (e.g., that has a synthetic depth-of-field effect applied), and/or managing media capture.
    Type: Application
    Filed: September 23, 2021
    Publication date: November 3, 2022
    Inventors: Behkish J. MANZARI, Graham R. CLARKE, Toke Jansen, Joseph A. Malia, Andre SOUZA DOS SANTOS, William A. SORRENTINO, III, Jeffrey A. BRASKET, Wayne LOOFBOURROW, Seyyedhossein MOUSAVI, Jens Jacob Pallisgaard, Paul Thomas SCHNEIDER, Joshua Blake Shagam, Piotr J. Stanczyk
  • Patent number: 11489390
    Abstract: A stator assembly includes an annular body extending about a central axis and a plurality of stator teeth extending axially from the annular body and spaced circumferentially about the annular body. The stator assembly includes at least one conduction coil and at least one bobbin configured to support the at least one conduction coil. The at least one bobbin is coupled to a first stator tooth such that the at least one conduction coil extends about the first stator tooth. The stator assembly further includes at least one insulation member configured to couple to a second stator tooth and extend into a slot between the second stator tooth and the at least one conduction coil. The at least one insulation member includes an end wall configured to cover the distal end of the second stator tooth when the at least one insulation member is coupled to the second stator tooth.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: November 1, 2022
    Assignee: Regal Beloit America, Inc.
    Inventors: Joseph Aaron Henry, Shirish Vatkar, Paul Nathanael Selking, Alan Jacob Manz, Don James Bray
  • Patent number: 11474123
    Abstract: A pitot tube includes an outer tube extending from a first tube end to second tube end, the second tube end defining a tip portion of the pitot tube, the tip portion including an inlet opening. A tube sleeve inside of the outer tube at least partially defines a tube passage extending from the first tube end to the second tube end. The tube sleeve includes a sleeve outer surface having a sleeve body portion having a first outer diameter and a sleeve tip portion located at the tip portion of the pitot tube. The sleeve tip portion has a second outer diameter smaller than the first outer diameter. A heating element is located between the outer tube and the tube sleeve at at least the sleeve tip portion.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: October 18, 2022
    Assignee: ROSEMOUNT AEROSPACE INC.
    Inventors: Robin Jacob, Guru Prasad Mahapatra, Paul Robert Johnson
  • Patent number: 11463894
    Abstract: Disclosed is a virtual base station capable of hosting multiple network operators and/or private networks in a single compute environment. The virtual base station includes a plurality of virtual baseband processors configured to communicate with the plurality of mobile network operators, a supervisor module, a fronthaul network interface configured to be coupled to one or more remote units, and a KPI (Key Performance Indicator) coordinator module coupled to the supervisor module and the one or more virtual baseband processors. The base station may have on or more CBRS (Citizens Broadband Radio Service) Daemons to act as a proxy for obtaining grants to CBRS channels and allocating the CBRS channels to the mobile network operators.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: October 4, 2022
    Assignee: John Mezzalingua Associates, LLC
    Inventors: Massimo Notargiacomo, Todd Landry, Jeffrey Masters, Roberto Orlandini, Jeffrey Courington, Francesco Foresta, Stephan Turner, Allesandro Pagani, Domenico Di Iorio, Kurt Jacobs, Patrick Henkle, Vishal Agrawal, Sasi Eswaravaka, Paul Stath
  • Patent number: 11445389
    Abstract: Disclosed is a virtual base station capable of hosting multiple network operators and/or private networks in a single compute environment. The virtual base station includes a plurality of virtual baseband processors configured to communicate with the plurality of mobile network operators, a supervisor module, a fronthaul network interface configured to be coupled to one or more remote units, and a KPI (Key Performance Indicator) coordinator module coupled to the supervisor module and the one or more virtual baseband processors. The base station may have on or more CBRS (Citizens Broadband Radio Service) Daemons to act as a proxy for obtaining grants to CBRS channels and allocating the CBRS channels to the mobile network operators.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: September 13, 2022
    Assignee: John Mezzalingua Associates, LLC
    Inventors: Massimo Notargiacomo, Todd Landry, Jeffrey Masters, Roberto Orlandini, Jeffrey Courlington, Francesco Foresta, Stephen Turner, Alessandro Pagani, Domenico Di Iorio, Kurt Jacobs, Patrick Henkle, Vishal Agrawal, Sasi Eswaravaka, Paul Stath
  • Patent number: 11416134
    Abstract: The present disclosure generally relates to user interfaces for altering visual media. In some embodiments, user interfaces capturing visual media (e.g., via a synthetic depth-of-field effect), playing back visual media (e.g., via a synthetic depth-of-field effect), editing visual media (e.g., that has a synthetic depth-of-field effect applied), and/or managing media capture.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: August 16, 2022
    Assignee: Apple Inc.
    Inventors: Behkish J. Manzari, Graham R. Clarke, Toke Jansen, Joseph A. Malia, Andre Souza Dos Santos, William A. Sorrentino, III, Saumitro Dasgupta, Wayne Loofbourrow, Seyyedhossein Mousavi, Jens Jacob Pallisgaard, Paul Thomas Schneider, Joshua Blake Shagam, Piotr J. Stanczyk, Hjalte Wedel Vildhoej
  • Patent number: 11418699
    Abstract: The present disclosure generally relates to user interfaces for altering visual media. In some embodiments, user interfaces capturing visual media (e.g., via a synthetic depth-of-field effect), playing back visual media (e.g., via a synthetic depth-of-field effect), editing visual media (e.g., that has a synthetic depth-of-field effect applied), and/or managing media capture.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: August 16, 2022
    Assignee: Apple Inc.
    Inventors: Behkish J. Manzari, Graham R. Clarke, Toke Jansen, Joseph A. Malia, Andre Souza Dos Santos, William A. Sorrentino, III, Saumitro Dasgupta, Mikko Berggren Ettienne, Wayne Loofbourrow, Seyyedhossein Mousavi, Jens Jacob Pallisgaard, Paul Thomas Schneider, Joshua Blake Shagam, Piotr J. Stanczyk
  • Publication number: 20220245431
    Abstract: A computer-implemented method of machine-learning. The method includes obtaining a dataset of 3D modeled objects representing real-world objects. The method further includes learning, based on the dataset, a generative neural network. The generative neural network is configured for generating a deformation basis of an input 3D modeled object. The learning includes an adversarial training.
    Type: Application
    Filed: December 27, 2021
    Publication date: August 4, 2022
    Applicant: DASSAULT SYSTEMES
    Inventors: Eloi MEHR, Ariane JOURDAN, Paul JACOB
  • Patent number: 11335006
    Abstract: An image segmentation system is discloses that provides one or more possible contours of a feature of an image, in parallel, that respectively correspond to different interpretations of the image. First, a relatively large set of possible contours are generated in accordance with an image segmentation algorithm. Subsequently, this set of possible contours is reduced to a few candidates reflecting representative solutions corresponding to one or more desired applications.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 17, 2022
    Assignee: MIM Software, Inc.
    Inventors: Hanlin Wan, Paul Jacobs, Jerimy Brockway, Jonathan Piper
  • Publication number: 20220057370
    Abstract: A chemical reactor is implemented on a substrate and has an inlet for receiving a fluid and/or a gas; a filter element for reducing or preventing that materials cause a blockage in the fluid supplied and/or the gas supplied in a part of the chemical reactor located further away; and a part located further away for transporting and/or processing the fluid and/or the gas. The part located further away has a depth dlow smaller than the depth dhigh of the inlet. The filter element has a first duct part and a second duct part; the first duct part is positioned closer up against the inlet than the second duct part, the first duct part is deeper than the second duct part, the first duct part has a diverging width and is free from pillar structures, and the second duct part is filled with filter pillars.
    Type: Application
    Filed: January 31, 2020
    Publication date: February 24, 2022
    Inventors: Jeff OP DE BEECK, Bo CLAEREBOUT, Paul JACOBS
  • Publication number: 20220053936
    Abstract: A seating unit system is provided to mount seats to a nose of a balcony. The seating unit system includes a balcony mount beam secured to the nose of the balcony. The balcony mount beam includes a front plate and a return. The front plate has an upwards extension. The seating unit includes one or more seats. Each seat has a balcony mount stanchion and a front rail socket connected to the balcony mount stanchion. The balcony mount stanchion includes a hook feature and a balcony mount beam bracket. The hook feature attaches to the upwards extension of the front plate and the balcony mount beam bracket attaches to the return. The front rail socket is configured to receive a front rail.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 24, 2022
    Inventors: Paul-Jacob Michael Richmond, Christian Harvie
  • Publication number: 20220048005
    Abstract: A chemical reactor is implemented on a substrate. The chemical reactor has multiple ducts for transporting a fluid and/or gas during use of the chemical reactor, in which the ducts optionally include pillar structures and at least one connection duct connected between two of the multiple ducts for transporting the fluid and/or gas from one duct to another. In the connection duct, a series of individual pillar structures are positioned behind each other in the longitudinal direction of the connection duct.
    Type: Application
    Filed: December 20, 2019
    Publication date: February 17, 2022
    Inventors: Jeff OP DE BEECK, Bo CLAEREBOUT, Wim DE MALSCHE, Paul JACOBS
  • Publication number: 20210270898
    Abstract: Examples described herein provide a computer-implemented method that includes initiating a logic built-in self-test (LBIST) of a device under test (DUT). The method further includes performing latch state counting using a multiple input signature register (MISR) of the DUT, the performing responsive to the MISR being in a counter mode. The method further includes performing a latch transition counting of latches of the DUT using the MISR of the DUT and a storage latch, the performing responsive to the MISR being in the counter mode. The method further includes performing a latch count comparison by comparing an output of the MISR responsive to the MISR being in the counter mode to an output of a count compare register, the output of the count compare register representing a desired MISR state.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 2, 2021
    Inventors: Franco Motika, Richard Frank Rizzolo, Paul Jacob Logsdon
  • Patent number: 11105853
    Abstract: Examples described herein provide a computer-implemented method that includes initiating a logic built-in self-test (LBIST) of a device under test (DUT). The method further includes performing latch state counting using a multiple input signature register (MISR) of the DUT, the performing responsive to the MISR being in a counter mode. The method further includes performing a latch transition counting of latches of the DUT using the MISR of the DUT and a storage latch, the performing responsive to the MISR being in the counter mode. The method further includes performing a latch count comparison by comparing an output of the MISR responsive to the MISR being in the counter mode to an output of a count compare register, the output of the count compare register representing a desired MISR state.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: August 31, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Franco Motika, Richard Frank Rizzolo, Paul Jacob Logsdon
  • Patent number: 11041519
    Abstract: A hook latch is provided for use with a tail chain hook, said hook having a curved outer spine, an inner surface, a hook end and an opening defined between the inner surface and the hook end through which a load can be hooked. The hook latch has a band for engagement about the outer spine of the hook and a plug positionable between the hook end and the inner surface of the hook and releasably engagable with the band to block the opening of the hook.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: June 22, 2021
    Inventor: Antoine Paul Jacob Gagnon
  • Publication number: 20210157963
    Abstract: A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests (“LBIST”) trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.
    Type: Application
    Filed: November 22, 2019
    Publication date: May 27, 2021
    Inventors: Sean Michael Carey, Richard Frank Rizzolo, Bodo Hoppe, Divya Kumudprakash Joshi, Paul Jacob Logsdon, Sreekala Anandavally, WILLIAM RURIK