Abstract: A neural codec includes a first simulated predictor for predicting a first block corresponding to a target block within a current frame, wherein the first block is predicted in accordance with the target block of the to-be-predicted current frame and pixels of neighbor blocks adjacent to the target block being input to the first simulated predictor, a second simulated predictor for predicting a second block corresponding to a target block using a reference block of a frame determined based on a prediction mode, wherein the second block is predicted in accordance with the reference block of a reference frame adjacent to the current frame and the target block being input to the second simulated predictor, and a selection network configured to select, based on the prediction mode, one of the first block and the second block as a predicted block.

Abstract: A wireless power transmission apparatus for wirelessly transmitting power to a wireless power reception apparatus is provided. The wireless power transmission apparatus includes a power transmitting circuit including a coil and at least one processor to control to transmit, via the power transmitting circuit, a pilot power with changing a frequency of the pilot power within a predetermined frequency range, obtain a magnitude of power wirelessly transmitted to a wireless power reception apparatus based on the transmitted pilot power, determine an operating frequency based on the obtained magnitude, and control to transmit, via the power transmitting circuit, a driving power having the operating frequency to drive the wireless power reception apparatus.

Abstract: A wireless power transmission apparatus for wirelessly transmitting power to a wireless power reception apparatus is provided. The wireless power transmission apparatus includes a power transmitting circuit including a coil and at least one processor to control to transmit, via the power transmitting circuit, a pilot power with changing a frequency of the pilot power within a predetermined frequency range, obtain a magnitude of power wirelessly transmitted to a wireless power reception apparatus based on the transmitted pilot power, determine an operating frequency based on the obtained magnitude, and control to transmit, via the power transmitting circuit, a driving power having the operating frequency to drive the wireless power reception apparatus.

Abstract: A power factor correction circuit and an electronic product including the same are disclosed. This technology configures a bridgeless circuit with no rectifier diode by using an additional switch, eliminating conduction loss due to the diode and reducing common mode EMI noise of the power factor correction circuit. A power factor correction circuit includes at least one inductor directly connected to an AC input stage, an output capacitor to smooth the output voltage, first switching elements to control current to store magnetic energy in the inductor, and a second switching element to maintain a substantially constant voltage between a ground voltage of an AC input stage and a ground voltage of an output stage.

Abstract: The present disclosure relates generally to a switch driving circuit and power factor correction circuit having the same, and more particularly, to a technology to provide a negative offset using Zener diodes to prevent malfunctions in driving a switch. The switch driving circuit to operate a switch implemented with a Field Effect Transistor (FET) includes a first Zener diode connected to a control input end of the switch; a capacitor connected in parallel with the first Zener diode; and second and third Zener diodes for providing a negative offset to fix a voltage applied between the gate and source of the switch to a negative value.

Abstract: The present disclosure relates generally to a switch driving circuit and power factor correction circuit having the same, and more particularly, to a technology to provide a negative offset using Zener diodes to prevent malfunctions in driving a switch. The switch driving circuit to operate a switch implemented with a Field Effect Transistor (FET) includes a first Zener diode connected to a control input end of the switch; a capacitor connected in parallel with the first Zener diode; and second and third Zener diodes for providing a negative offset to fix a voltage applied between the gate and source of the switch to a negative value.

Abstract: A power factor correction circuit and an electronic product including the same are disclosed. This technology configures a bridgeless circuit with no rectifier diode by using an additional switch, eliminating conduction loss due to the diode and reducing common mode EMI noise of the power factor correction circuit. A power factor correction circuit includes at least one inductor directly connected to an AC input stage, an output capacitor to smooth the output voltage, first switching elements to control current to store magnetic energy in the inductor, and a second switching element to maintain a substantially constant voltage between a ground voltage of an AC input stage and a ground voltage of an output stage.