Abstract: The present invention provides a grill 10 for use in electrical equipment comprising a fan. The grill 10 comprises a substantially planar portion 90 that provides protection for (and indeed from) the blades of a fan and a handle 100 that provides means by which the grill may be held. The substantially planar portion 90 may comprise an opening 94 that facilitates stacking of a plurality of like grills 10.

Abstract: Various embodiments of a heat sink assembly are disclosed. In one embodiment, the heat sink assembly includes a processor mounted onto a circuit board; a heat sink located in thermal contact with the processor at the side of the processor opposite circuit board; and an electromagnetic shielding member located between the circuit board and the heat sink. The electromagnetic shielding member is releasably attached to the circuit board. Additionally, or in the alternative, the heat sink is biased toward the processor by a load spring and the electromagnetic shielding member is configured to provide a spring force between the circuit board and the heat sink, counter directional to the bias from the load spring.

Abstract: A cooling module is provided for an electrically powered apparatus. The cooling module comprises a non-volatile memory arranged to store a module identifier code for the module.

Abstract: An indicator assembly for a computer system can comprise a light guide for directing light from an indicator light source to an exterior panel of the computer system. The assembly can also comprise a photodetector configured to receive a portion of the light transmitted by the light guide. The photodetector can produce a signal representative of the portion of light received. For example, the photodetector may produce a signal representative of the color and/or intensity of the portion of light received. Using the signal representative of the portion of light received, components such as a controller can test for the presence of faults.

Abstract: There is provided a computing apparatus. The computing apparatus has first and second computing elements and a heatsink thermally coupled to each of the first and second computing elements. A portion of the heatsink thermally coupled to the first computing element is thermally separated from a portion of the heatsink thermally coupled to the second computing element by a region having a reduced thermal conductivity.

Abstract: A dirty memory is operable to store dirty indicators, each dirty indicator being settable to a given value indicative that a page of memory associated therewith has been dirtied. The dirty indicators are stored in groups with each group having associated therewith a validity indicator computed from the dirty indicator values of the group. The control logic is operable on reading a group to compute a validity indicator value based on the dirty indicator values for the group to determine the integrity of the group. The integrity can be confirmed by comparing the computed validity indicator value to a validity indicator value read for the group. Where the value read and the value computed compare equal, it can be assumed that the dirty indicator values of the group are correct. Preferably the validity indicator is a parity indicator. Although parity does not provide for error correction, parity has the advantage that minimal overhead is needed for computation and storage.

Abstract: A computer system comprising at least two processing sets. Each processing set includes main memory. A bridge connects the processing sets. At least a first processing set further including a dirty memory having dirty indicators for indicating dirtied blocks of the main memory of the first processing set. The bridge includes a direct memory access controller that is operable to copy blocks of the first processing set indicated in the dirty memory to the main memory of another processing set. The processors do not, therefore, need to carry out the copying, whereby the processor overhead associated therewith can be avoided, increasing the efficiency of memory reintegration. The direct memory access controller can be arranged to search the dirty memory for dirty indicators indicative of dirtied blocks. Alternatively, the dirty memory can include control logic operable to search the dirty memory for dirty indicators indicative of dirtied blocks.

Abstract: A dirty memory subsystem includes storage operable to store redundant copies of dirty indicators. Each dirty indicator is associated with a respective block of main memory and is settable to a predetermined state to indicate that the block of main memory associated therewith has been dirtied. By providing redundant storage for the dirty indicators, any difference between the stored copies of the dirty indicators can be considered as indicative of memory corruption, for example as a result of a cosmic ray impact. As the different copies can be stored in different locations, it is unlikely that a cosmic ray impact would affect all copies equally. If a difference between the stored copies is detected, then the dirty indicator can be take as being unreliable and remedial action can be taken. For example, it can be assumed that a block of main memory has been dirtied if any of the copies of the dirty indicator has the predetermined state.

Abstract: An electromagnetic (EM) shielding assembly includes an electrically conductive shielding portion and one or more electrically conductive protrusions for engaging with respective conductive apertures in a circuit board. The electrically conductive protrusions can be in electrical communication with the EM shielding portion. The protrusions can enable the EM shielding assembly to be attached to a circuit board in a computer system while also providing an electrical connection to logical ground. Further components, for example a heat sink that may be in electrical communication with the EM shielding portion, may thereby also be connected to logical ground.

Abstract: A media drive mount includes first and second first and second channels open at one end for receiving locating protrusions on a media drive. The locating protrusions can, for example, be screwed onto the media drive mount. Resilient detents are provided in the channels to co-operate with the resilient detents. The resilient detents can be configured to provide resistance during insertion and removal of the media drive, the former being used to provide positive locating of the media drive, and the latter to hold the media drive in the mount. Mounting and demounting of the media drive in the mount can be achieved without the use of tools.

Abstract: The present invention provides a grill 10 for use in electrical equipment comprising a fan. The grill 10 comprises a substantially planar portion 90 that provides protection for (and indeed from) the blades of a fan and a handle 100 that provides means by which the grill may be held. The substantially planar portion 90 may comprise an opening 94 that facilitates stacking of a plurality of like grills 10.

Abstract: A dirty memory that includes dirty indicators settable to indicate dirtied pages of memory is provided with control logic operable automatically to interrogate the dirty memory to identify dirty indicators that are set. Implementing the control of the dirty RAM in hardware or firmware enables interrogation of the dirty RAM to identify set dirty indicators in a rapid and reliable manner. The control logic can advantageously be operable to interrogate the dirty memory word-by-word to determine words including a set bit. A comparator can be provided for comparing bits of a word to a predetermined value to determine where a dirty indicator is set. The comparison could be performed serially for bits within a word, but it is advantageously done in parallel for the bits of the word. For example, by using associative memory, the interrogation of the dirty memory could be effected associatively in parallel to determine words including a word with a set bit.

Abstract: A dirty memory for a computer system is configured hierarchically. This provides for more rapid identification of pages of memory that have been dirtied and require attention. For example for the reintegration of an equivalent memory state to the memories of respective processing sets in a fault tolerant computer following a lockstep error. The dirty memory includes at least two levels. A lower level includes groups of dirty indicators, each dirty indicator being settable to a given state indicative that a page of memory associated therewith has been dirtied. At least one higher level includes dirty group indicators settable to a predetermined state indicative that a group of the lower level associated therewith has at least one dirty indicator in a state indicative that a page of memory associated therewith has been dirtied. There can be more that two layers. Logic controls the operation of the hierarchical dirty memory.

Abstract: There is provided a heatsink assembly. The heatsink assembly comprises: a processor mounted onto a circuit board; a heatsink located in thermal contact with the processor at the side of the processor opposite circuit board; and an electromagnetic shielding member located between the circuit board and the heatsink. The electromagnetic shielding member is releasably attached to the circuit board. Additionally, or in the alternative, the heatsink is biased toward the processor by a load spring and the electromagnetic shielding member is configured to provide a spring force between the circuit board and the heatsink, counter directional to the bias from the load spring.

Abstract: A dirty memory is operable to store dirty indicators, each dirty indicator being settable to a given value indicative that a page of memory associated therewith has been dirtied. The dirty indicators are stored in groups with each group having associated therewith a validity indicator computed from the dirty indicator values of the group. The control logic is operable on reading a group to compute a validity indicator value based on the dirty indicator values for the group to determine the integrity of the group. The integrity can be confirmed by comparing the computed validity indicator value to a validity indicator value read for the group. Where the value read and the value computed compare equal, it can be assumed that the dirty indicator values of the group are correct. Preferably the validity indicator is a parity indicator. Although parity does not provide for error correction, parity has the advantage that minimal overhead is needed for computation and storage.

Abstract: A dirty memory that includes dirty indicators settable to indicate dirtied pages of memory is provided with control logic operable automatically to interrogate the dirty memory to identify dirty indicators that are set. Implementing the control of the dirty RAM in hardware or firmware enables interrogation of the dirty RAM to identify set dirty indicators in a rapid and reliable manner. The control logic can advantageously be operable to interrogate the dirty memory word-by-word to determine words including a set bit. A comparator can be provided for comparing bits of a word to a predetermined value to determine where a dirty indicator is set. The comparison could be performed serially for bits within a word, but it is advantageously done in parallel for the bits of the word. For example, by using associative memory, the interrogation of the dirty memory could be effected associatively in parallel to determine words including a word with a set bit.

Abstract: A dirty memory for a computer system is configured hierarchically. This provides for more rapid identification of pages of memory that have been dirtied and require attention. For example for the reintegration of an equivalent memory state to the memories of respective processing sets in a fault tolerant computer following a lockstep error. The dirty memory includes at least two levels. A lower level includes groups of dirty indicators, each dirty indicator being settable to a given state indicative that a page of memory associated therewith has been dirtied. At least one higher level includes dirty group indicators settable to a predetermined state indicative that a group of the lower level associated therewith has at least one dirty indicator in a state indicative that a page of memory associated therewith has been dirtied. There can be more that two layers. Logic controls the operation of the hierarchical dirty memory.

Abstract: A computer system comprising at least two processing sets. Each processing set includes main memory. A bridge connects the processing sets. At least a first processing set further including a dirty memory having dirty indicators for indicating dirtied blocks of the main memory of the first processing set. The bridge includes a direct memory access controller that is operable to copy blocks of the first processing set indicated in the dirty memory to the main memory of another processing set. The processors do not, therefore, need to carry out the copying, whereby the processor overhead associated therewith can be avoided, increasing the efficiency of memory reintegration. The direct memory access controller can be arranged to search the dirty memory for dirty indicators indicative of dirtied blocks. Alternatively, the dirty memory can include control logic operable to search the dirty memory for dirty indicators indicative of dirtied blocks.

Abstract: A volatile field programmable gate array (FPGA) having a configurable logical structure portion that is configurable with encrypted configuration data stored external to the FPGA in configuration data memory. On FPGA reconfiguration, for example on power-up, the encrypted configuration data is supplied to an input of the FPGA. In the FPGA, the configuration data is first decrypted by a decryption algorithm embedded in logic, the algorithm using as an operand a decryption key stored in the FPGA in a non-volatile memory, for example EEPROM. The decrypted configuration data is then distributed to the volatile functional portion of the FPGA in a conventional manner. The functional portion may be SRAM. With this design, unauthorized reading of the configuration data of the FPGA by observation of the stream of configuration data transmitted to the FPGA from the external memory, for example during power-up, will only result in encrypted configuration data being obtained.

Abstract: A bridge for a multi-processor system includes bus interfaces for connection to an I/O bus of a first processing set, an I/O bus of a second processing set, and a device bus. A bridge control mechanism is configured to provide geographic addressing for devices on the device bus and to be responsive to a request from a device on the device bus for direct access to a resource of a processing set to verify that an address supplied by the device falls within a correct geographic range. A different geographic address range can allocated to each of a plurality of device slots on the device bus. A different geographic address range can also be allocated to the processor set resources (e.g., processor set memory). An address decoding mechanism maintain geographic address mappings, and verifies geographic addresses for direct memory access. The geographic address mappings can be configured in random access memory of the bridge. A slot response register is associated with each slot on the device bus.