Abstract: A semiconductor non-volatile memory device is disclosed which is based on the use of Fowler-Nordheim electron tunneling to charge and discharge the isolated gates of the storage cells. The disclosed memory device includes circuitry capable of verifying the threshold level of written storage cells and rewriting only those cells whose threshold is outside a desired threshold range. The disclosed circuit has the further advantage of being able to load data words and verify cell contents simultaneously by utilizing both ends of the bit lines.

Abstract: A distribution charge pump is disclosed that reduces leakage from a VPP node where a programming voltage (VPP) is provided. The distribution charge pump includes a pump section and a biasing network. The pump section, in response to input signals at 0V or VCC, generates corresponding output signals at 0V or VPP, respectively. Typically, VCC can be between 2V and 5V and VPP can be between 11V and 15V. The pump section includes two n-channel transistors that bootstrap each other to cooperatively pull up the output node to VPP in response to an input signal of VCC. When the charge pump is active, one of the transistors, a native-mode device, transfers charge from the VPP node to an internal node where charge is stored by a capacitor. The biasing network reduces leakage current from the VPP node through the native-mode transistor when the charge pump is inactive.

Abstract: A high speed memory cell current measurement circuit uses an on-chip reference current circuit that generates a reference current Iref. The reference current circuit includes a first current source transistor. An on-chip current comparison circuit has a second current source transistor that is coupled to the first current source transistor so as to mirror the reference current Iref at a fixed current ratio WR. The current comparison circuit has a current connection path connecting the second current source transistor to a memory cell in the semiconductor memory device whose current is to be compared with Iref/WR. The memory cell is selected from the cells in a memory array using the device's on-chip address decoder circuitry. An on-chip result generation subcircuit, coupled to the current connection path between the second current source transistor and the memory cell, produces a Result signal that indicates whether current flowing through the memory cell is more or less than Iref/WR.

Abstract: A 5V generator circuit is disclosed that generates a reliable 5V signal for use in integrated circuits from the available VPP or VCC supplies for a wide range of VPP and VCC voltages. When VCC is greater than approximately 4V, the generator circuit generates the 5V signal directly from VCC. When VCC is less than approximately 4V and VPP is greater than approximately 4V but less than about 9V, the generator circuit generates the 5V signal directly from VPP. When VCC is less than approximately 4V and VPP is greater than approximately 9V, the generator produces the 5V signal at approximately half of the voltage level of the VPP signal. When both VCC and VPP are less than about 4V, the 5V signal is generated at the too-low VCC level.

Abstract: A semiconductor non-volatile memory device is disclosed which is based on the use of Fowler-Nordheim electron tunneling to charge and discharge the isolated gates of the storage cells. Furthermore, the disclosed memory device includes global decoder circuitry capable of passing either positive or negative voltages to a set of global word lines controlling-local decoder circuitry, said local controller circuitry in turn controlling row select lines or local word lines. Each local decoder controls a multiplicity of word lines. The local decoder circuitry is located in physical proximity to specific memory sectors thus resulting in an improved layout of the decoder circuitry and enabling the selection of one of the multiplicity of word lines within said sector by means of electrical control lines. The electrical control lines select one of the multiplicity of rows within a memory sector and deselect all the remaining rows. Logic control circuitry is provided to control the logic of the local row decoders.

Abstract: An erase state machine controls the process of erasing all the memory cells in a selected sector of a flash memory array. The erase state machine includes a sequence of states for controlling generation of high positive and negative voltages, and application of the high positive voltage to all word lines in the selected sector and application of the high negative voltage to the source nodes of all memory cells in the selected sector. A sequence of two discharge states are used to discharge the high voltages from the word lines and source nodes. If an erase operation is aborted while high voltages are being generated, the erase state machine asynchronously transitions to the first of the two discharge states, and then transitions to the second discharge state and then back to a final inactive state during successive state machine clock cycles.

Abstract: A program drain voltage pump is provided that employs multiple pumping sections that are adaptively controlled to provide a pumped drain voltage (VD) that rises smoothly and rapidly to an optimum VD level for programming EPROM or flash memory cells and maintains VD at the optimum level with minimal ripple. The pumping sections are configured to pump a common VD node that is coupled to the drains of the EPROM or flash memory cells. Each pumping section is driven by a clock signal whose pulses are out of phase with the clock signals driving the other pumping sections. All of the clock signals have roughly the same frequency. Due to the staggered clocks, each pump is activated during a different respective time period, which smooths out VD.

Abstract: A distribution charge pump is disclosed that provides a high voltage output that can be used to write or erase EEPROM cells. The charge pump is enabled by a high (VCC) input signal, which is input to a pair of always-on pass transistors. The output of one of these pass transistors turns on a third transistor whose source is tied to an internal node that is coupled to one terminal of a MOS capacitor and the gate of a fourth transistor. The other terminal of the MOS capacitor is tied to a clock signal and the source and drain of the fourth transistor are tied respectively to the charge pump output and a high voltage power supply node (VPP). The capacitor stores charge on the internal node when the clock signal goes high and discharges when the clock signal goes low. Due to this discharge, the voltage at the internal node drops, which causes the third transistor to turn on and supply charge to the internal node, preventing the complete discharge of charges stored during the positive phase of the clock cycle.

Abstract: An on-chip positive and negative high voltage wordline x-decoding system for EPROM/FLASH is disclosed wherein three transistors are required for each wordline. The x-decoding system minimizes system latch-up by separating the positive and negative high voltage portions of the system. The high-voltage portion of the x-decoding system includes a native mode PMOS transistor fabricated in a N-well on a common P-substrate and a high-voltage NAND gate that supplies a control signal to the gate of the PMOS transistor. In response to a variable power signal (which is at O VDC in erase mode, VCC in a read mode, and approximately +10 VDC in program mode) and the control signal (which is low when the memory cell is selected and the system is in read or program modes), the positive portion pulls the selected word line up to VCC and +10 VDC in read and program modes, respectively.

Abstract: A double erase control circuit is disclosed for use with an EEPROM/flash memory system wherein each memory cell can be read, erased or programmed based, in part, on the voltage level of a word line coupled to the gate of each of the memory cells. A host selectively erases flash memory cells by placing 0 VDC on the word lines and a large positive voltage (10.4 VDC to 10.8 VDC) on an array virtual ground supply (VVSS) line while the drains of the memory cells float. The voltage and current on the VVSS line are simultaneously controlled using voltage and current control circuitry that are responsive to a high erase signal that is asserted by the host during an erase operation. When the erase signal is high, the voltage control circuitry uses a comparator, a stable reference voltage (1.28 VDC) derived from a band-gap reference and a feedback loop to maintain VVSS at the target source erase voltage (i.e., 10.4 VDC to 10.8 VDC).