Abstract: A method and apparatus are provided for performing on-board, in-circuit, and/or wafer level scan-based testing of integrated circuits. With the apparatus and method, one or more sequential storage elements, e.g., flip/flops, are coupled to combinational logic and are configured to have an additional port for receiving a scan mode signal. The scan mode signal sets the sequential storage element into one of two modes of operation: static mode in which the sequential storage element's output does not change on a falling edge of a scan enable signal or a transitional mode in which the sequential storage element's output is permitted to change on the falling edge. With sequential storage elements configured in this manner, a configuration scan is performed to set certain ones of the sequential storage elements into a static mode and other sequential storage elements into a transitional mode. A test pattern is then applied to the sequential storage elements and a pattern capture cycle is commenced.