Patents by Inventor Paul Joseph Jordan
Paul Joseph Jordan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6701484Abstract: A register for a computer processor removes the parity check from the critical path of CPU operation, and delays the parity check to the next immediate clock cycle. The register has a memory array, and read and write decoders for accessing the memory array using select lines. The select lines are also connected to read and write address latches which are used to index a parity bit array. When a value is written to, or read from, the memory array, its corresponding parity bit is calculated and either stored in the parity bit array (for a write operation), or compared to an existing parity bit array entry (for a read operation). The parity check is performed on a copy of the value contained in a read data latch or a write data latch. Each data latch has an input connected to a respective read or write port of the memory array. The latches delay the parity check by only one cycle.Type: GrantFiled: August 11, 2000Date of Patent: March 2, 2004Assignee: International Business Machines CorporationInventors: Paul Joseph Jordan, Peter Juergen Klim
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Patent number: 6658534Abstract: The mechanism to reduce instruction cache miss penalties by initiating an early cache line prefetch is implemented. The mechanism provides for an early prefetch of a next succeeding cache line before an instruction cache miss is detected during a fetch which causes an instruction cache miss. The prefetch is initiated when it is guaranteed that instructions in the subsequent cache line will be referenced. This occurs when the current instruction is either a non-branch instruction, so instructions will execute sequentially, or if the current instruction is a branch instruction, but the branch forward is sufficiently short. If the current instruction is a branch, but the branch forward is to the next sequential cache line, a prefetch of the next sequential cache line may be performed. In this way, cache miss latencies may be reduced without generating cache pollution due to the prefetch of cache lines which are subsequently unreferenced.Type: GrantFiled: March 31, 1998Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Steven Wayne White, Hung Qui Le, Kurt Alan Feiste, Paul Joseph Jordan
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Patent number: 6629170Abstract: A multi-stage byte lane selectable bus. In a preferred embodiment, the bus in performance monitor mode includes a plurality of byte lanes and a selection mechanism. The selection mechanism acquires, from a plurality of signals, a subset of those signals, which are desired to be monitored, and places this subset of signals on the byte lanes that are input to the PMU. The number of the plurality of signals that potentially may be monitored is greater than the number of byte lanes and is also greater than the number of PMU counters.Type: GrantFiled: November 8, 1999Date of Patent: September 30, 2003Assignee: International Business Machines CorporationInventors: Joel Roger Davidson, Michael Stephen Floyd, Paul Joseph Jordan, Judith E. K. Laurens, Alexander Erik Mericas, Kevin F. Reick
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Patent number: 6336182Abstract: A method and system for aligning internal operations (IOPs) for dispatch are disclosed. The method and system comprise conditionally asserting a predecode based on a particular dispatch slot that an instruction is going to be placed. The method and system further include using the information related to the predecode to expand an instruction into at least one dummy operation and an IOP operation whenever the instruction would not be supported in the particular dispatch slot.Type: GrantFiled: March 5, 1999Date of Patent: January 1, 2002Assignee: International Business Machines CorporationInventors: John Edward Derrick, Lee Evan Eisen, Paul Joseph Jordan, Robert William Hay
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Patent number: 6061777Abstract: One aspect of the invention relates to a method for operating a processor. In one version of the invention, the method includes the steps of dispatching an instruction; determining a presently architected RMAP entry for the architectural register targeted by the dispatched instruction; selecting the RMAP entries which are associated with physical registers that contain operands for the dispatched instruction; updating a use indicator in the selected RMAP entries; determining whether the dispatched instruction is interruptible; and updating an architectural indicator and a historical indicator in the presently architected RMAP entry if the dispatched instruction is uninterruptible.Type: GrantFiled: October 28, 1997Date of Patent: May 9, 2000Assignee: International Business Machines CorporationInventors: Hoichi Cheong, Paul Joseph Jordan, Hung Qui Le, Soummya Mallick
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Patent number: 5999992Abstract: This invention relates to a system and method for adapting the ports of computing elements in transferring data between computing elements on a network. Ports of the computing elements are interconnected for data transfer through a switch complex. The interconnected ports are adapted to cooperate together in transferring the data. Data which is ordinarily designated to be transferred through one port of a computing element may be transferred through a different port.Type: GrantFiled: October 12, 1995Date of Patent: December 7, 1999Assignee: International Business MachinesInventors: Gregory Frederick Grohoski, William Rudolph Hardell, Jr., Paul Joseph Jordan, Oscar Reid Mitchell, Tung Manh Nguyen, Yonjae Rim
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Patent number: 5983341Abstract: A data processing system indicates that an instruction does not have available data because of a cache miss or because of a non-cache-miss delay. When the instruction is not able to access the available data and a cache miss results, instructions which are dependent on the issued instruction are not issued. However, if the load execution is delayed because of a non-cache-miss delay, then the instructions which are dependent on the issued instruction are also issued in anticipation of a successful load instruction execution in a next timing cycle. Through the use of this issuing mechanism, the efficiency of the data processing system is increased as an execution unit is better able to utilize its pipeline.Type: GrantFiled: April 25, 1997Date of Patent: November 9, 1999Assignee: International Business Machines CorporationInventors: Hoichi Cheong, Paul Joseph Jordan, Hung Qui Le
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Patent number: 5974524Abstract: According to one aspect of the invention, a method is provided for maintaining the state of a processor having a plurality of physical registers and a rename register map which stores rename pairs that associate architected and physical registers, the rename register map having a plurality of entries which are associated with the physical registers, individual entries having an architected register field, an architected status bit and a history status bit.Type: GrantFiled: October 28, 1997Date of Patent: October 26, 1999Assignee: International Business Machines CorporationInventors: Hoichi Cheong, Paul Joseph Jordan, Quan Nguyen, Hung Qui Le
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Patent number: 5875326Abstract: During operation of a pipelined data processing system, an interruptible instruction table is used to store target identifiers associated with instructions which may result in speculative execution. During operation of the interruptible instruction table, a pointer, referred to as a completing instruction buffer entry pointer, points to a bottom of the interruptible instruction table if that table includes any instruction. An entry at the bottom of the interruptible instruction table is a next instruction to complete. This entry includes a target identifier, referred to as a non-speculative-non-interruptible TID, may be used to release resources held for all prior executed instructions. The data processing system determines the value of the non-speculative-non-interruptible TID to ensure that order determination is preserved and provides a true speculative execution point.Type: GrantFiled: April 25, 1997Date of Patent: February 23, 1999Assignee: International Business Machines CorporationInventors: Hoichi Cheong, Paul Joseph Jordan, Hung Qui Le
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Patent number: 5805906Abstract: In a data processing system using a number of registers for processing instructions, a method and apparatus for writing information to the registers. Ports are accessed for writing back to processor registers, information ("results") resulting from and associated with executing instructions. Certain of the results are stored for restoring to the registers. In response to an interruption at least one of the ports is accessed for restoring stored results to the registers. Accesses to the ports are arbitrated in response to comparing writeback and restoration results. A result includes identification of the instruction the result is associated with (a "TID"), and a register that is targeted by the result (a "TR"). The comparing includes comparing TID's and TR's for the results.Type: GrantFiled: October 15, 1996Date of Patent: September 8, 1998Assignee: International Business Machines CorporationInventors: Hoichi Cheong, Hung Qui Le, Paul Joseph Jordan
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Patent number: 5805849Abstract: A data processor assigns a unique identifier to each instruction. As there are a finite number of unique identifiers, the identifiers are reused during execution of a program within the data processing system. To maintain an age relationship between instructions executing in the pipeline processor, a methodology is developed to ensure that reused identifiers are properly designated as being younger than their older but larger in magnitude, counterparts. To resolve this issue, assume that the identifier assigned to each instruction has N bits, and therefore, there are 2.sup.N identifiers to be assigned to instructions in the program. The 2.sup.N identifiers are separated into 2.sup.m banks. In addition to assigning identifiers to each instruction, an identifier assignment logic circuit within the pipeline processor provides a global signal that indicates which bank is a youngest bank from which the identifiers are assigned to a remaining portion of the pipeline processor.Type: GrantFiled: March 31, 1997Date of Patent: September 8, 1998Assignee: International Business Machines CorporationInventors: Paul Joseph Jordan, Brian R. Konigsburg, Hung Qui Le, Steven Wayne White