Patents by Inventor Paul K. Boyer

Paul K. Boyer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4902640
    Abstract: A mixed bipolar-CMOS self-aligned process and integrated circuit provide a high performance NPN bipolar transistor in parallel to fabrication of a PMOSFET and an NMOSFET. Gate and base contacts are formed in a first polysilicon layer. The base contacts are implanted with P+ ion concentrations for diffusing base contact regions of the substrate in a later drive-in step. Source and drain contacts and emitter contacts are formed in a second polysilicon layer. The source and drain contacts are formed as a unit and then separated into discrete contacts by a spin-on polymer planarization and etch-back procedure. Lightly-doped lateral margins of the source, drain and base regions are ion-implanted in an initial low concentration (e.g. about 10.sup.13 atoms/cm.sup.2). The gate and base contact structures serve as a mask to self-align the implants. Then, the gate and base structures are enclosed in an oxide box having sidewalls.
    Type: Grant
    Filed: August 19, 1987
    Date of Patent: February 20, 1990
    Assignee: Tektronix, Inc.
    Inventors: Jack Sachitano, Hee K. Park, Paul K. Boyer, Gregory C. Eiden, Tadanori Yamaguchi
  • Patent number: 4826782
    Abstract: An intermediate structure in the fabrication of a metal-oxide semiconductor field-effect transistor is made from a substrate of p+ silicon having an elongate insulated gate structure on its main face. First and second areas of the main face are exposed along first and second opposite sides respectively of the gate structure. Donor impurity atoms are introduced into the substrate by way of at least the first area of the main face, to achieve a predetermined concentration of electrons in a region of the substrate that is subjacent the first area of the main face. The gate structure is opague to the impurity atoms. A sidewall of silicon dioxide is formed along the first side of the gate structure, whereby a strip of the first area of the main face is covered by the sidewall and other parts of the first area remain exposed adjacent the sidewall.
    Type: Grant
    Filed: April 17, 1987
    Date of Patent: May 2, 1989
    Assignee: Tektronix, Inc.
    Inventors: Jack Sachitano, Paul K. Boyer, Hee K. Park, Gregory C. Eiden
  • Patent number: 4509451
    Abstract: Applicants have invented a new low temperature method (50.degree. C. to 500.degree. C.) to deposit and grow microelectronic thin films using cold cathode electron beams to initiate and sustain both gas phase and surface chemical reactions. The new method uses electron beams generated by glow discharge electron guns. Secondary electrons are emitted from these electron guns following ion and fast neutral bombardment upon cathode surfaces and secondary electrons so formed are accelerated in the cathode sheath.Our method uses the plasma generated electron beams to decompose reactant molecules directly by electron impact and indirectly by the vacuum ultraviolet radiation generated following rare gas electron collisions in the beam region. The reactant molecules can be in the gas phase or adsorbed on substrate surfaces. The electron beams are spatially confined and excite only a localized region above the substrate so that direct plasma bombardment of the substrate is avoided.
    Type: Grant
    Filed: March 29, 1983
    Date of Patent: April 9, 1985
    Assignee: Colromm, Inc.
    Inventors: George J. Collins, Lance R. Thompson, Jorge J. Rocca, Paul K. Boyer